Worst Case Differential Input clock jitter for TFP401A

Peter Murphy

Other Parts Discussed in Thread: TFP401A

According to the TFP401A data sheet the "Worst-case differential input clock jitter tijit" is 50ps.

The two notes indicate by characterization and the measurement details.

Does the jitter change with bandwidth?
Is it full bandwidth or does it not matter the bandwidth for this measurement? I am using a pixel clock of 74.5MHz much lower than the 165MHz limit.

Thanks.

Peter

over 11 years ago

0 Elias Villegas M. over 11 years ago

TI__Guru* 76130 points

We are investigating this and we'll reply soon.

Regards.

0 Diego Cortes over 11 years ago

TI__Mastermind 36085 points

Hello Peter,

This worst case, is indeed the worst jitter result on all the bandwidth and across all the combinations of supply voltage and temperature.

In fact, the jitter changes across the bandwidth and is highly dependent on the PCB layout design, however as I mentioned before, the 50ps shall be the worst result under the recommended operating conditions.

Best regards,

Diego.

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Worst Case Differential Input clock jitter for TFP401A