[ DS90UB928 ] Power Up Sequence

Kenichiro

Mastermind 9165 points

[ DS90UB928 ] Power Up Sequence

Hi,

I have couple of questions regarding power up sequence of DS90UB928.

As like below, would that be okay that PDB, OE and OSS_SEL to ramp up simultaneously?

Also, after output is enabled, is there a possibility that DS90UB928 output kind of noise?

From the table.1 "Output State Table" in the datasheet, I do understand that when PDB, OE and OSS_SEL are tied to high, and then there is no input "signal" appeared on RIN+/-, there should not be any output from device.

However if there is a "noise" which large enough for device to detect it, device would output something.

Is it correct?

Thanks,

Ken

over 11 years ago

0 Jason Blackman over 11 years ago

TI__Genius 14015 points

Hi Ken,

It is fine if PDB, OEN and OSS_SEL all ramp at the same time. OEN and OSS_SEL can be toggled in real time -- the value at start-up doesn't latch the mode. IDx and MODE_SEL are read once after PDB goes high and are latched, so you want the voltages on those pins to be stable before PDB ramps up. It looks like that would be the case for you.

In order for the deserializer to start outputting data, the internal PLL has to lock to the incoming FPD-Link III signal. If there is noise on the line, it would have to be the right voltage levels as well as periodic within the FPD3 frequency range for the PLL to lock, which seems very unlikely.

Let me know if you have any more questions.

Thanks!
Jason Blackman

0 Kenichiro over 11 years ago in reply to Jason Blackman

Mastermind 9165 points

Hi Jason,

Thank you for your reply!

I would like to share the back ground with you,

can you please dorp an e-mail to me?

Thanks,

Ken

tanaka-k (at) clv.macnica.co.jp

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[ DS90UB928 ] Power Up Sequence

[ DS90UB928 ] Power Up Sequence