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LMH0376 - SD3GDA-III eval board - doesn't seem to do much

Richard Woodham1
Prodigy 210 points
Other Parts Discussed in Thread: LMH0046, LMH1218

I've posted a similar comment as a reply elsewhere, but this seems more to the High Speed Interface Forum.  When I examine the jitter on the output of this reclocker board it doesn't seem much better than the input.  

The conditions I am have are:

Jumpers as per User Guide.

SMPTE 292 SDI input (colour bars test pattern with excessive jitter)

Carrier detect LED is lit.

1.485Gbps LED is lit.

Fault LED on LMH0309 (sic) is lit.

SDO output measured 2us downstream of trigger point shows ~0.5ns jitter (should be better than 130ps)

Is the reclocker chip in bypass mode, somehow?

  • 0
    TI__Expert 3175 points

    Hi Richard,

    With trigger=2us, I suspect you are seeing the contribution of lower frequency jitter from the video source.

    Retimer is capable to remove or reduce the high frequency jitter. Low frequency input jitter within the PLL bandwidth will pass through.

    regards,

    TK Chin

  • 0 in reply to T.K. Chin
    Prodigy 210 points

    I thought about this over the weekend and came to the same conclusion myself.  The question is, can anything be done to improve the situation?  

    We were planning on using the LMH0046 to re-clock our video signal (SMPTE-292, which specifies jitter down to 100kHz).  The LMH0046 datasheet is quite 'light' on information regarding jitter performance.  In particular the only indication for what the loop filter capacitor value should be is the application circuit which has 56nF.  Is it possible to increase this to improve the low frequency jitter performance, without upsetting the PLL loop stability?  Is there a design equation?

    Regards,

    Richard

  • 0 in reply to Richard Woodham1
    TI__Expert 3175 points

    Hi Richard,

    Receiver with CDR is able to track the low frequency jitter from the incoming data, so it is considered "not harmful". On the other hand, CDR is not able to track the high frequency jitter, and thus is more critical.

    I do not recommend to change the reclocker's PLL bandwidth. Reducing the bandwidth will hurt its ability to track the lower frequency jitter.

    The downstream receiver's CDR is able to track the low frequency jitter, and should not be a problem.

    regards,

    TK Chin

  • 0 in reply to T.K. Chin
    Prodigy 210 points

    Will the LMH1218 clean up the low-frequency jitter better?

    Regards,

    Richard

  • 0 in reply to Richard Woodham1
    TI__Expert 3175 points

    Hi Richard,

    All CDR will have similar transfer function, depends on where the PLL bandwidth is set. Low frequency jitter will pass through, and high frequency jitter (above the PLL bandwidth) will be attenuated. The LMH1218 will be similar.

    I think the problem is to reduce the low frequency jitter of the clock used for the data source.

    regards,

    TK Chin

  • 0 in reply to T.K. Chin
    TI__Guru* 93670 points
    Hi Richard,

    I like to add some additional comments.

    The low frequency noise source, mentioned by TK, can be identified using spectrum analyzer. Usually high low frequency content, aside from the data pattern, could be coming from power supply switching noise or perhaps common mode noise on the input signal.

    As noted by TK, it is not a good idea to change or reduce the loop bandwidth since this could reduce jitter tolerance as well.

    Regards,,nasser