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TLK105 / register setting for Compliance Test of 100Base Duty Cycle Distortion TEST

Guru 20090 points
Other Parts Discussed in Thread: TLK105
Hello,
 
Our customer are operating the compliance test of 100BASE TX.
They are facing test failure on "100Base Duty Cycle Distortion TEST".
 
In this test, TLK105 should output the data of "010101".
Can we clear the this test by changing register of TLK105?
 
If we must set the register for compliance test, please let me know its.
 
Best Regards,
Ryuji Asaka
  • How is this test being conducted?  The test can be run using scrambled idles, at least for some Ethernet Compliance software packages. 

    What board is being used for the testing?  Is this a board that you have designed and manufactured?

    Patrick

  • Hello,
     
    The board is the designed at the our customer.
    They use "TF-GBE-ATP" for compliance test.
    They set the bit12 of Addr:0x0000 to "0".
     
    Please see the attached file as thier waveform of compliance test.
    In their test, tx waveform amplitude is varied.
    Duty Cycle Distortion TEST is failed  if  the trigger  is applied at the amplitude variation point.
     
    http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/903/2335.20140526_5F00_TLK105-tx-waveform.pdf
     
    Could you please let me know any idea for the improvement ? 
    If you need more information, please let me know.
     
    Best Regards,
    Ryuji Asaka
  • Hello Patrick san,

    I got the additional information.

    They use "TDSET3" as Ethernet compliance test software.And they change the below register from default value.
    Then, they could pass the Ethernet compliance test.

    Could you please let me know whether these change is no problem?

    -for MDI
    Address 0x0000 : Auto negotiation Enable(bit12) set  to "0"
    Address 0x0019 : Auto MDIX Eanable(bit15) set to "0"
    All other bits are default value.
    -for MDIX
    Address 0x0000 : Auto negotiation Enable(bit12) set  to "0"
    Address 0x0019 : Auto MDIX Eanable(bit15) set to "0" ,  Force MDI/X(bit14) set to "1".
    All other bits are default value.

    Best Regards,

    Ryuji Asaka

  • These changes are no problem.  The effect of these changes is to force 100M operation and output scrambled idles in MDI and MDIX mode.  This is how we test DCD with the Tektronix TDSET3 compliance software.

    Patrick

  • Hello Patrick san,

    Thank you for the reply.
    I understood.

    Best Regards,
    Ryuji Asaka