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Interfacing Altera DE4 with TI external chip.

Other Parts Discussed in Thread: DS32EL0421, TLK6002

Hi,


I am trying to implement a SERDES (SCAN12100,TLK6002, DS32EL0421, or something similar) to serialize a 20 bit, 100MHz parallel input to 6.25Gbps. I have an Altera DE 4 board with a STRATIX IV, and I would like to interface it with one of these chips. First of all, how do I make sure that my FPGA can definitely be interfaced with these chips? For example, how do I know which of the chips is most compatible with my board.

Secondly, I do not have experience or expertise in designing these boards. I was wondering if you could suggest any assembly company that help solder the chip on the pcb.


Thank you very much in advance.

  • Hi Nurul,


    The TLK6002 will work fine for application.


    An FPGA is made up of GPIO pins that can be programed to be an input or an output with some firmware built around them. The main concerns to be thinking of when selecting an FPGA to go around your PHY is voltage IO levels of the GPIO pins, the number of GPIO pins needed, and also the clocking architecture of the FPGA. For example does your PHY require 24 1.8V IO pins and your FPGA only has 12 1.5V and 12 1.8V or vise versa. Beyond this you will need to make sure that you understand the IO pin functionality on the PHY and program your FPGAs firmware around this to generate interrupts or what ever else is specific to your system.


    When I was in college I simply did a Google search of board houses and I was able to come up with a handful of companies to support my design needs.

  • Thank you very much for the reply.

    I think TLK 6002 will work fine for my system. I am however concerned about whether I should design a PCB layout with the chip or I should buy the TLK 6002 EVM kit. 

    If I decide to print a board with just the chip on the surface, I am worried about matching the impedance since I am looking to get really high speed data out. Do you have any suggestion?

  • Hi Nurul,


    I admit that designing and laying out your first high speed board can be a overwhelming task but with a little bit of preparation and guidance it is definitely an achievable goal.

    Attached are the layout files for the TLK6002 so you can see first hand how we did it (cadence file). Also, attached is an application report that discusses high speed layout guidelines. Please let me know what other questions you have and I will be glad to help.

    6866.High Speed Layout Guidelines.pdf

    1452.TLK60x2_091709.brd