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DS110DF410 - Reference Clock

Kawai
Guru 19785 points

Other Parts Discussed in Thread: DS110DF410

Hi Team,

Could you please tell me about the REFCLK of DS110DF410 ?

I am understanding that the device uses REFCLK 25MHz in the internal counter which monitors if the input datarate is inside the PPM range that is set in the register.

During the system operation, when there are such cases like below for the REFCLK, what happens or how does the device behave ?
Our customer worries if there would be a case the device would go into dead lock ;  the device would not be able to re-lock to the input signal.

REFCLK Cases

- Case1)  25MHz --> varies higher than 25MHz --> returns to 25MHz stable.
- Case2)  25MHz --> varies lower than 25MHz --> returns to 25MHz stable.
- Case3)  25MHz --> missing some clock cycles --> returns to 25MHz stable.
- Case4)  25MHz --> noise occur on 25MHz  --> returns to 25MHz stable.
- Case5)  25MHz --> lose REFCLK --> returns to 25MHz stable.

The device may  lose CDR LOCK in some cases, however after the REFCLK returns to the normal 25MHz, I believe the device will re-lock to the input signal and return to normal operation.

Could we have your opinion to this question ?

Thanks and Best Regrds,
Kawai

  • 0
    TI__Expert 3175 points

    Hi Kawai san,

    The 25MHz reference clock is used as a "time-base" during the adaptation process. The clock's phase and jitter behavior does not affect the retimer's jitter performance, but we expect the 25MHz to be stable, no glitch and within +-100ppm.

    regards,

    TK Chin

  • 0 in reply to T.K. Chin
    Guru 19785 points

    Hi T.K. -san,

    Thank you for the explanation.

    Please let me change my question. Could you please tell me about the followings ?

    Q1)
    Is there any problem if 25MHz REFCLK is lost, disturbed or varied to different frequency during the normal operation ? What happens to the device ?

    Q2)
    Can DS110DF410 keep CDR lock, when 25MHz REFCLK is lost, disturbed or varied to different frequency ?

    As 25MHz is used for the internal counter, I thought the device may judge the input data as outside the programmed range in the above cases.

    Q3)
    I believe that as long as REFCLK returns to stable 25MHz, DS110DF410 could operate normally; relock to the input signal ,  even if there were disturbance or variation. Is my recognition correct ?

    Best Regards,
    Kawai

  • 0 in reply to Kawai
    TI__Intellectual 1705 points

    Hi Kawai-san,

    The 25MHz clock is used to help the CDR to lock to the input signal so it can perform a fast cap search and check the ppm count with the programed VCO frequency and lock faster to the input signal.  The 25MHz clock is only used during the locking process as an internal calibration, it is not used by the VCO to generate the retimed output. During normal operation (CDR is locked), the 25MHz clock is not needed and if it is lost the CDR would still remain locked.

    In the refmode=3, the 25MHz clock is required and within the +/-100ppm for the CDR to lock. The default ppm tolerance on the high speed input signal is +/-1000ppm and there is ppm checking prior to declaring CDR lock.

    If the 25MHz REFCLK is stable the CDR will try to lock too the input signal. After the CDR is locked, the 25MHz is no longer needed. If for some reason that the CDR to loses lock; eg. lost of input signal or high amount of jitter that cause the eye to close below the HEO, VEO lock threshold, the 25MHz is used again to relock to the input signal. We do not know when the losing lock can occur, so it is best to use a stable clock from an oscillator.

    Regards,

    Michael

  • 0 in reply to Michael Hinh
    Guru 19785 points

    Hi Michael-san,

    Thank you for the detail explanation.

    I understood that REFCLK will be only needed in the process where DS110DF410 is tries and until CDR LOCK.

    Best Regards,
    Kawai