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DS80PCI402 compatibility with Pericom's PI2EQX5804

Other Parts Discussed in Thread: DS80PCI402, DS80PCI800

Hello,

I have a custom PCIe external adapter board with the DS80PCI402 that I'm trying to connect to an off-the-shelf PCIe adapter in the host PC, which uses Pericom's PI2EQX5804. Pericom's ReDriver has a similar receiver detection mechanism as the TI part and I can clearly see the "ping" from the off-the-shelf adapter coming all the way through to my external PCIe adapter board (just before it enters the TI ReDriver). However, the Pericom part just isn't able to actually detect the TI part, even though I manually configured the TI's differential input to run in manual RX-Detect mode, that is to have  the inputs be in 50-Ohm termination state. I can also not see any change to the "ping" signal (which is what the Pericom part needs in order to detect the receiver) whenever I set the TI's differential input to 50-Ohm termination manually (either via I2C or external pin). What I noticed though in the datasheet is that the TI ReDriver essentially terminates the differential inputs via 50 Ohm to VDD whereas the Pericom part terminates its differential inputs with 50 Ohms to ground. On top of that Pericom's ReDriver also terminates its differential outputs with 50 Ohms to VDD, the TI ReDriver datasheet remains silent about that.

So what I was wondering whether the TI ReDriver is actually compatible with Pericom's ReDriver as my feeling is it is not due to the discrepancy in input/output termination of both peers.

Can you weigh in on that? If that's the case, is there an easy workaround to still get it to work? I was hoping that since this is all about the standardized PCIe protocol I wouldn't have to worry about this...

Thanks,

Steffen

  • Steffen,

    The DS80PCI402 was designed to the PCIe standard on receive detection, so I do not expect there is any issue. The link is AC coupled, so it does not matter whether the 50-ohm termination to VDD or to GND. The AE of this part will look into this case and get back to you soon.

    Regards,

    TK Chin

  • Steffen,

    This is not a typical PCIe application, usually devices like the DS80PCI800 are not cascaded in a single PCIe channel between Host - Endpoint or Switch.   

    The DS80CPI800 receiver detection works with inputs terminated to VDD or to GND due to the AC coupled requirement of PCIe. Receiver detection should be seen on both P and N signals.  In order for a valid "detection" to occur, both P and N sides must independently detect the Rx termination.

    I have a couple intial questions:

    1. Do you also see Rx detection pings originating from the DS80PCI402 going back to the Host PC?

    2. Are you measuring from the signal line to GND or differentially across P/N lines?

    3. Do you have any oscilloscope waveforms that can be shared?

    It would be useful to understand the register programming sequence and the pin control levels used to setup the DS0PCI402 to help ensure everything is correct.

    Regards,

    Lee

  • Hello Lee,

    thanks a lot for your response. In the meanwhile I was actually able to sort out the receiver detection problems described earlier. Just to answer your questions for completeness:

    1. I was never really able to catch the "ping" event back to the host PC as the repeater must have detected it right away and switched to normal transfer mode.

    2. Unfortunately the lack of appropriate measurement equipment does not allow me to probe differentially as I only have a high-speed single ended probe, measuring the signal line to GND. Good enough for me just for go/no go checking

    3. I don't have any scope waveforms to share at the moment.

    Having solved all these problems, your initial comment is making me scratch my head. I may have been unclear when I described the situation but I thought I was using these repeaters similar to what is considered a "Typical Application" on page 2 of the DS80PCI402 datasheet. The only difference is that instead of a backplane I'm actually looking at a PCIe external cable (2m) connection the root complex from the host PC to the external PCIe endpoint.

    It would be very helpful if you could elaborate on what exactly you were trying to point out.

    Thanks,

    Steffen