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[ DS90UB914A ] Registers

Kenichiro
Mastermind 9165 points

[ DS90UB914A ] Registers

Hi,
When I go through the register list of DS90UB914A, some registers seem not to have enough description.
Can you help me to understand correctly?
<0x00[0], I2C Device ID/Deserializer ID Select>:
It says that "0: De-Serializer Device ID is set using address coming from CAD". What does this "CAD" stand for?
<0x01[5], Reset/ANAPWDN>:
Can you explain a little detail?
Which "analog blocks" are powered off with this bit? also during this state, which functions are still active? (What about video transmission and back channel communication?)
And, what is the benefit for customer?
 
 
<0x03[5:4], General Configuration1/VDDIO Control & Mode>:
From the description, it seems that bit5 selects whether device detect VDDIO voltage automatically or user specify it. If user prefer to select by himself, bit5 is set to “0”, then select voltage from bit4. Correct?
On top of that, on customer board, this VDDIO voltage is 1.8V until all of initialization finish, then turn to 3.3V. For this configuration, is there any limitation and/or restrictions?
 
 
 
<0x04[7:0], EQ Feature Control>:
Hex value in the descriptions are all 0x0F... this should be same as 0x4E, EQ Value. Correct?
 
 
<0x06[0], SER ID/Freeze Device ID>:
There is no details for 914, which 913 has. Is this same as 913?
 
 
 
<0x1F[6:5], Mode and OSS Select/OEN Select and OSS Select>:
These two registers gives same function as described Table.11 Output States, correct?
 
<0x23[7:0], General Purpose Control/GPCR>:
How does this register work? need to care?
 
 
<0x42[1:0], CRC Force Error/Force Back Channel Error>:
These are used to test serializer can detect some errors which put on back channel communication intentionally. 
 
 
<0x4D[6], AEQ Test Mode Select/AEQ Bypass>:
This gives user to select EQ values (0x04) rather than using AEQ value, set by device automatically.
Correct?
 
 
Thank you for your support in advance.
Regards,
Ken
 
  • 0
    TI__Genius 13475 points

    Ken

    Thank you for all of your work looking at this datasheet.   I am preparing a detailed reply which I will be posting shortly.

    Mark

  • 0 in reply to Mark Sauerwald88474
    Mastermind 9165 points
    Hi Mark,
     
    Thank you for your support.
    Feel free to communicate with me, if further information is necessary.
    I can share business background.
     
    tanaka-k(at)clv.macnica.co.jp
     
    Thanks,
    Ken
  • 0 in reply to Kenichiro
    TI__Intellectual 2060 points

    Hi Ken,

    <0x00[0], I2C Device ID/Deserializer ID Select>:

    I am not sure what CAD stands for but if this is set to 0 the device ID is loaded from the resister divider on the IDx pins.  See Figure 37 and Table 10 for more details on the 914A IDx pins.  If this bit is set to 1 the device id can be programmed by I2C to reg 0x00 bits [7:1].

    <0x01[5], Reset/ANAPWDN>:

    This is a low power mode that powers down the 914A FPDIII transceiver.  Video and backchannel are not available in this mode.  The benefit is that the registers are still available to a local I2C master.  If you do not need to transmit across the link but would like to read/write registers.

    <0x03[5:4], General Configuration1/VDDIO Control & Mode>:

    You are correct about the operation of these registers.  We recommend that the VDDIO reach its full value before the other voltage rails begin to ramp.  The datasheet is currently being update to reflect this.  I would not recommend changing the VDDIO voltages during operation.

    <0x04[7:0], EQ Feature Control>:

    The 0x0F for all settings is a typo.  The table should read:
    0x0F = ~8 dB
    0x1F = ~11 dB
    0x3F = ~12.5 dB
    0x7F = ~14 dB
    0xFF = ~16 dB

    <0x06[0], SER ID/Freeze Device ID>:

    If bit [0] is 0 then [7:1] will be auto loaded from the Serializer ID through the forward channel.  Setting bit [0] to 1 will allow you to write the I2C address to bits [7:1] and keeps it from being overridden by auto loading.

    <0x1F[6:5], Mode and OSS Select/OEN Select and OSS Select>:

    By default Mode, OEN and OSS are set by pin strapping/resister divider.  These registers allow control of Mode, OEN and OSS by I2C rather than pin strapping.  OEN_OSS Override has to be set to 1 for the register values to be used rather than the pin strapping for both OEN and OSS.  Mode_Override has to be set to 1 in order for the mode to be set by bits [1:0] rather than resistor divider.  OEN and OSS are the same as the inputs in Table 11.  There is no register override for PDB, this will have to be set through pin strapping.

    <0x23[7:0], General Purpose Control/GPCR>:

    This register has no effect. You're allowed to overwrite and use for anything you want.

    <0x42[1:0], CRC Force Error/Force Back Channel Error>:

    Setting either one of these should cause errors to appear in the paired 913A reg 0x2A when in BIST mode.  This is often used as a sanity check to make sure the device is truly in BIST mode.

    <0x4D[6], AEQ Test Mode Select/AEQ Bypass>:

    Correct.

    Let me know if you have any more questions.

    Regards,

    Mike

  • 0 in reply to Michael Mellitt
    Mastermind 9165 points
    Hi Mike,
     
    Thank you so much for your support! This is great help for me.
     
    BTW, with regards to typo and missing description, should I send feedback to "Submit Documentation Feedback"?
    (Every page has a link  to send feedback, below is embedded in the UB914A datasheet.)
     
     
    Or it's great, if you can share with your team.
     
    Thanks,
    Ken
  • 0 in reply to Kenichiro
    TI__Genius 13475 points

    Ken

    Mike and I are in the process of revising the '913A datasheet now, so the comments in this thread have already been taken care of.  If there are additional things in the datasheet that you feel need attention, then either the 'Submit Documentation Feedback' button, or in this forum are fine.

    Mark

  • 0 in reply to Mark Sauerwald88474
    Mastermind 9165 points
    Hi Mark,
     
    Thanks! that would be fine!
     
    Regards,
    Ken