This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi Ken,
There isn't actually a sleep mode, it's more of a standby mode where the 925 is waiting for a valid PCLK. The internal oscillator will be used to maintain communication with the deserializer in this state. t_PLD is the time from 'sleep' or standby to the output being driven.
During the time while the 925 is trying to lock to the PCLK, the outputs will be disabled.
I'm not sure what you mean by limitation when PDB is enabled. Can you elaborate?
The delay from PDB going low to the output being disabled is on the order of 10-20ns.
Thanks,
Jason
Hi Jason,
Thank you for your support and sorry that my reply being late.
"limitation", mean that, I just wondered whether any of conditions (timing, input signal appearance etc) should be taken when PDB is enabled. From your reply, I understood that PDB can be enabled anytime it's necessary.