[ DS90UB928 ] Delay from RIN to TxCLKOUT/TxOUT

Kenichiro

[ DS90UB928 ] Delay from RIN to TxCLKOUT/TxOUT

As drawing above, datasheet specifies the delay from enabling OEN to output ready, and disabling PDB to enabling LOCK, however can you please let me know the delay from RIN appearance to data/clk ready, RIN disappearance to data/clock disable?

Please let me know, if you have any questions. Thank you for your support in advance.

Regards,

Ken

over 11 years ago

0 Mark Sauerwald88474 over 11 years ago

TI__Genius 13475 points

The delay from Rin appearance to TxCLKOUT will be dominated by the lock time of the device which is worst case about 40ms, but is typically much shorter, at about 6ms.

I am not certain about the amount of time from Rin disappearing until TXCLKOUT disappears should be much shorter.

0 Kenichiro over 11 years ago in reply to Mark Sauerwald88474

Mastermind 9165 points

Thanks, Mark!!

Regards,

Ken

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[ DS90UB928 ] Delay from RIN to TxCLKOUT/TxOUT

[ DS90UB928 ] Delay from RIN to TxCLKOUT/TxOUT