I'm using TFP401 to read from HDMI and process the signals in FPGA , when i watch the signals in chipscope the DE ( Data enable ) is active when Vsync is both high and low , but DE should be high During Both Vsync and Hsync are high .
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I'm using TFP401 to read from HDMI and process the signals in FPGA , when i watch the signals in chipscope the DE ( Data enable ) is active when Vsync is both high and low , but DE should be high During Both Vsync and Hsync are high .
When transitioning out of blanking(When DE transitions from Low to High), the current state of the HSYNC and VSYNC signals are locked (Regardless of polarity) until DE transitions again into blanking (DE High to Low). The TFP401 will only output changes in HSYNC and VSYNC during blanking.