Team,
Can you see if there is something wrong with the SN65LVDS34D ibis model?
When I try to get Hyperlynx to simulate it driving a 163MHZ clock it only shows a single rising edge coming out?
Screen capture of his simulation is attached.
Please let me know what further information is needed.
Regards,
Amy
Amy,
The LVDS34 IBIS model is fine and passes IBIS checks. I've checked both LVDS (differential) and TTL I/Os in Cadence SigXplorer 16.2 and found them working as expected. I've attached a circuit topology and results for a 163MHz clock driven from the LVDS34 TTL output to the LVDS387 TTL input. Since the customer is simulating with the IBIS model of the LVDS34 device along with an IBIS model of an FPGA device on the receive side, I'd suggest to do the following tests to know exactly which IBIS model is having issues:
1. Run the same simulation in Hyperlynx but with the IBIS model of the FPGA TTL input replaced with the IBIS model of the TTL input of the LVDS387 device (just like what is shown in the attached picture). The IBIS model of the LVDS387 device can be obtained from the TI website (http://www.ti.com/litv/ibs/sllc031a).
2. Run the same simulation in Hyperlynx but with the IBIS model of the TTL output of the LVDS34 device replaced with an IBIS model of any other TTL output that is known to work well. For example, an IBIS model of the TTL outputs of the same FPGA can be used if already proven to work well.
Please let us know the outcome of the above tests so that we can provide further assistance.
Best regards.
Hassan.
