TUSB3210 - problems with USB detection

Hello Eduardo,

We are looking to your question. We will reply soon.

Best Regards,

Alexis Cortes.

Hi Alexis,

Do you have any news on the subject?

Best regards,

Eduardo Siridakis

Hello Eduardo,

Sorry for the delayed response. From the scope captures you posted, it appears that you are not following the reset timing requirements for the TUSB3210 (section 4.2 of the datasheet), on the failing case it can be seen that the clock is not valid during the reset window. Please make sure you are following all the next reset's timing requirements:

1. The minimum reset pulse duration is 100μs. At power up, this time is measured from the time the power ramps up to 90% of the nominal VCC until the reset signal exceeds 1.2 V. 

2. Clock must be valid during the last 60 μs of the reset window. 

3. Device must be ready to respond to the host within a100 ms.

4. Due to 3, it is recommende that the device should come out from reset within the first 30ms after power-up.

Additionally:

- Could you please post your schematics (or send it to alexis.cortes@ti.com) so we can review it?

- Could you take scope captures of a failing and a passing case and post it? Instead of probing PUR, could you probe VCC?

Note: On one of the boards you are using the combination R=100K/C=1uF, try changing the 100K resistor for a 15K and see if that helps.

Best Regards,

Alexis Cortes.

Hello Alexis!

Thank you for the attention. 

I see that the reset's timing requirements aren't being followed in the failing cases, but it seems to me that is the TUSB thats's not exciting the crystal properly, judging by the 1.8VDD signal, the clock becomes valid at the moment this signal goes up. Correct me if I'm wrong, but reading the datasheet I understood that the 1.8VDD pin is an input for core supply when the TUSB is on suspend, but "During normal operation, the internal 3.3- to 1.8-V voltage regulator of the TUSB3210 is enabled and provides power to the core". This makes me think that the TUSB excites the crystal when the core is supplied, and by some means it's not functioning properly.

The first image on the topic shows a passing case and we can see that the 1.8VDD signal goes up properly and so does the clock.

Seems also strange to me that 1.8VDD goes up exactly when the PUR signal goes down in the failing cases.

I'll try to get the scope captures you asked for, probing  VCC instead of PUR, and see what I can do about the schematics.

P.S.: About the RC combination, changing the 100K resistor to 15K would significantly reduce the reset rising time and we have observed that this initialization problem on TUSB ocurred a lot more often when we used the 33K/470nF combination, so we changed the 33K resistor to 200K to make the rising time on these board similar to the ones with 100K/1uF. Despite all that, I'll follow your suggestion to see what happens and report any changes in the scenario.

Best regards!

Eduardo Siridakis

Hello again Alexis, sorry for taking so long to reply.

I have the scope captures that you asked for. I'm gonna divide them in three categories and two sub-categories just to organize things. The 3 categories are: Board 1, Board 2 and Board 2 with 15k resistor, as you have suggested. The two sub-categories are passing case and failing case.

Board 1 is the one with 200k and 470nF RC on the reset pin and Board 2 is the one with 100k and 1uF RC on the reset pin. I have sent the schematics to you email. 

On all the captures the signals are as follow: Yellow for RESET, Blue for CLOCK, Pink for 1.8VDD and Green for VCC (3V3).

BOARD 1 - Passing case:

BOARD 1 - Failing case:

BOARD 2 - Passing case:

BOARD 2 - Failing case:

BOARD 2 with 15k resistor - Passing case:

BOARD 2 - Failing case:

As we can see, the behavior seems a little bit different from the captures I've shown in an earlier post, but the issue remains essentially the same in my opinion: The 1.8VDD signal drops making the CLOCK invalid and then everything goes back to normal but the TUSB is not recognized as an USB device. I haven't probed the PUR pin but as we saw in the earlier captures is that it goes low and doesn't rise anymore.

About the 15k resistor, the behavior remained the same and, as we have also observed on Board 1 with a 33k resistor, reducing the reset rising time this way makes the failing cases occur more often.

Sorry for the long post. I'll be awaiting you considerations!

Best Regards!

Eduardo SIridakis

I forgot to mention: We can also see that the reset rising time reduces significantly in the failing cases, as if there was some current leakage to the reset pin.

Hello Eduardo,

Your inquiry is now been handled via e-mail.

Best Regards,

Alexis Cortes.