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General Questions about USB3.0 and the TUSB1310A

Nick O
Prodigy 90 points
Other Parts Discussed in Thread: TUSB1310A

Hi,

I am a relatively young engineer with only a few years of design experience under my belt.  With that said, I've never worked with USB chipsets before. Recently, the group that I work for, asked me to work on designing a USB interface that allows for maximum bandwidth to talk to a board and chip that we're developing.

As such, with a little bit of homework, I found that Texas Instruments has a possible solution for us in the TUSB1310A USB Transceiver chip. I was wondering a couple of things, which I couldn't understand clearly from my datasheet investigation.

The first thing I wasn't sure about was regarding the maximum bandwidth that the chip can handle. Based on my naive understanding, there are two 16-bit buses, each operating at 250MHz (one for input and one for output data). My interpretation of this was that this means that the maximum bandwidth that the bus can handle is 4Gbps on each bus. Is my understanding of this correct? If so, then why/how can USB 3.0 specify that it can have data rates up to 5Gbps? Does this chip not support the full capability of the protocol?

Alternatively, this thought also spawned another question. Do the buses operate fully independently? Does that mean that one could theoretically get 8Gbps total bandwidth if their inputs and outputs weren't too dependent on each other or operated in parallel?

My other question is with regards to the PIPE interface. Based on some googling, I understand that it is a standard interface that Intel has specified for the PHY layer of the PCI Express.  With that said, how complicated is it to design some logic circuitry to interface with this bus/interface?

Lastly, what kinds of things should I be looking for in the datasheets to help me properly understand the chip and how to best design the interface to it so that we can optimize bandwidth? The group that I am working for will be processing a lot of data and so having as high-speed of an interface as possible is crucial.

  • 0
    TI__Guru* 76130 points

    Hello,

    The USB3.0 5Gbps represent raw bits, then, the USB protocol encodes the raw data and adds some overhead and send it via packets or symbols. So if you have a byte of data, the USB protocol will add several bits to your data and send it at 5Gbps, so you can see that your data throughput is not going to be 5Gbps.

    The PIPE interface of the TUSB1310A send two symbols through the 16-bit interface so it can support the USB 3.0 signaling rates.

    The 16-bit TX and 16-bit RX buses are independent but you can't make a 32-bit bus since they are only-output and only-input respectively.

    i recommend you to get the PIPE interface specification, you will likely need a 250MHz FPGA as well.

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 90 points

    We are actually trying to design our own asic that will talk to the USB chip directly.  As such, I have already gotten the PIPE specification, but wasn't sure how hard it is to design to it, as an interface.

    Do you have any insight regarding the difficulty of this type of a task?  Or is the TUSB1310A chip typically interfaced with an FPGA?  If it is interfaced with an FPGA, do you know what kinds of pad delays others who have designed this might be experiencing?  We really want to maximize our bandwidth, and as such, if we have to use an FPGA, we don't want it to slow down our data transmission process.

  • 0 in reply to Nick O
    TI__Guru* 76130 points

    Hello,

    We have only interfaced our TUSB1310A with FPGAs but it could be interfaced also with an ASIC.

    The FPGA pad delays depend on the FPGA that is selected and which of its pins are used. We did not have any great difficulty getting PIPE to work, especially not for a device with a single USB port.

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 90 points

    Hi,

    I've been scouring through much of the documentation (the datasheet, the PIPE specification, and the implementation guide) and I'm still a little confused about some stuff.

    In order to provide a little context, so that perhaps you might be able to help me make the best design decisions, I'll give you a high-level overview of our project. We are building a chip that will be generating a LOT of data.  As a lab, we are creating a chip that can simulate neural spikes and as such will be transmitting hundreds millions of spikes per second, where each spike is up to 2B (16 bits) of data.  As such, we need something that can handle at least 3Gbps of data throughput, but ideally we don't want to be limited by the USB chip at all.  We will only have one USB port and it will be connected to a host computer (through USB SuperSpeed).  The computer will take the packets being sent by the board of chips and visualize the information.  In parallel, we will also be generating spike packets on the host computer and send that information down to the chip/board.

    The first thing that I'm a little confused about is regarding how many IO pins I would need to interface to my ASIC and/or FPGA.  I know we need at least 38 IO Pins (16 for TX, 16 for RX, 2 for TX Control and 2 for RX Control, 1 for RX Valid, and 1 for PCLK).  The ones that I'm more confused about are the other control and status signals.  Is it required, for instance, for us to have the TX_DETRX_LPBK signal?  Below is my understanding; can you confirm whether this is accurate or wrong?

    Signal Name Connected to Notes/Usage/Questions
    PHY_MODE 0/1 PCB Set PHY_MODE1 to 0 and PHY_MODE0 to 1
    PHY_RESETN PCB/External Switch or ASIC When this signal is low, the chip resets
    TX_DETRX_LPBK ? When do I want to use this signal?
    TX_ELECIDLE ASIC Use this to disable Tx lines passing through, but is this necessary to have?  If so, under what circumstance would I use this?
    RX_ELECIDLE ? When and how do I use this signal?
    RX_STATUS PCB (or ASIC) Use to show what went wrong.  I can connect this to the ASIC if I want the ASIC to do some error handling, but that will complicate the logic...
    POWER_DOWN1/0 PCB As per the paragraph below, fix both of these to 0, to keep the state at P0.  How does this work during Reset when the state goes to U2?
    PHY_STATUS PCB (or ASIC) Similar to RX_STATUS, not necessary unless we want to do something once we know the status
    TX_ONESZEROS Nothing Not necessary because we aren't worried about compliance testing
    TX_DEEMPH 1/0 ?? What is de-emphasis exactly is this?  I have found that we should set it to a lower dB setting to offset high frequency noise on longer connections.  Does this apply to the PIPE side of the communication or is the default 01b an ok setting?
    TX_SWING PCB Set to 0 for Full Swing b/c we don't care about low-power operation
    RX_POLARITY PCB Set to a jumper for flexibility, but otherwise, don't invert
    RX_TERMINATIONS ?? I can't figure out what exactly these terminations are referring to.
    ELAS_BUF_MODE PCB Fix this value to 0 for half full buffer mode for maximum bandwidth (based on what I understood of some other reading online)

    From a design perspective, we won't really need the power down functionality of the USB chip, because my assumption is that in order to have the fastest throughput possible, the USB chip must be in the P0/U0 power state.  We are also not going to be operating using a battery, so we don't have any reason to turn the power to a lower consumption state.

    Any comments, answers, or notes regarding the table above would be much appreciated!

    N

  • 0
    Prodigy 20 points

    Hi,

    5Gbps => 16bit(Tx, Rx Data Width) --> 8b10b encoding/decoding(Functional Block Diagram in Datasheet)

                     --> 20bit x 250MHz = 5000M = 5Gbps ^^

  • 0 in reply to Nick O
    TI__Guru* 76130 points

    Hello, please see my comments to your table:

    PHY_MODE These can be left floating
    PHY_RESETn Correct, there is also another signal named RESETn which resets all the internal logic and bring all the terminals to its default state and care must be taken for a proper power-up, refer to Section 3 on datasheet.
    Terminal PHY_RESETn only reset the interface between the LLC and the PHY.
    TX_DETRX_LPBK With this signal the LLC tells the PHY to start a receiver detection operation, and also when to transmit LFPS.
    TX_ELECIDLE The LLC tells the PHY to put the USB SS TX lines in electrical idle, it also is used to tell the PHY when to transmit LFPS.
    Note that eventhough you are not going to put the PHY in power saving mode, the USB protocol may decide to put the USB lines in electrical idle.
    RX_ELECIDLE Tells the LLC a detection of electrical idle on the USB SS RX lines.
    RX_STATUS Correct, it shows that something went wrong, but it also tells when a SKIP ordered set was added or removed and this is required for a proper function of the USB protocol.
    POWER_DOWN1/0 Can be hardwired to 00b
    PHY_STATUS This is not only used for power down states, it is also used to tell the LLC the completion of several functions.
    TX_ONESZEROS Correct, required only for compliance test.
    TX_DEEMPH 1/0 Selects the de-emphasis of the signals going from the LLC to the PHY, can be hardwired.
    TX_SWING Correct
    RX_POLARITY Not exactly, this signal tells the LLC that the USB device connected at the other end has a polarity inversion on its USB lines.
    So you have to connect this signal because you don't know how is the other USB device be.
    RX_TERMINATIONS The LLC uses this signal to control the anble/disable of the USB receiver terminations of the PHY.
    ELAS_BUF_MODE Correct