XIO3130 SRST function for downstream port

Terry Wu

Expert 1680 points

Dear Sirs,

Would you kindly explain what's downstream port ( CLK / PCIe Tx / PERST ) behavior when set this bit

from default "0" to "1" ?

Many thanks !

0 Elias Villegas M. over 11 years ago

Hello,

The DNx_PERST will be held low for 80-100ns causing a fundamental reset to the downstream device.

Regards.

0 Terry Wu over 11 years ago in reply to Elias Villegas M.

Expert 1680 points

Dear Elias,

Do you mean set this bit will cause DNx_PERST hold "low" only 80~100ns and DNx_PERST will hold "high"automatically ?

Will DNx_REFCLK get same behavior ?

Many thanks your help !

0 Elias Villegas M. over 11 years ago in reply to Terry Wu

Correct,

There will be a low-pulse on the DNx_PERST. DNx_REFCLK will have the same behavior.

Regards.

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