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Trace delay on GMII clock signal for DP83865

Prad1
Genius 3825 points
Other Parts Discussed in Thread: DP83865

Hi

We need some clarification on GMII design layout on DP83865.

Will it be OK if we use the Equal-length trace for all the clock and data lines for GMII(1000Mbps) interface?

In case of RGMII connection in the DP83865 datasheet mentions that
"additional trace delay of greater than 1.5 ns is added to the associated clock signal".

Can we assume that the same requirement doesn't apply for the GMII interface?
Looking into the datasheet there is no specific mention saying GMTCLK clock be
delayed with respect to TXD[0..7] data.

Best Regards
Prad

  • 0
    TI__Mastermind 31600 points

    Absolutely correct.  There is no requirement for GMII to include additional delay. 

    Note that the DP83865 can support some internal delay for RGMII operation.  There is additional information in the RGMII section of the datasheet.  The two implementations are referred to as 3COM mode and HP mode.

    Another helpful resource would be the design and layout guide.  This is available at:

    http://www.ti.com/lit/pdf/snla058

    Patrick