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DS25BR110 suitable when the Eye Diagramm shows only +-50V

Other Parts Discussed in Thread: DS25BR110

I have an LVDS similar Signal with 325Mbps. The open Eye is only +-50mV at the receive side.

Is the DS25BR110 suitable to convert the signal to LVDS level. In the datasheet from the DS25BR110 the Input Threshold is +-100mV, but at the sample pictures in the datasheet the eye is complete closed.

  • Hi Bernd,

    Thanks for your patience as we work through posts preceding the U.S. Labor Day holiday. The input threshold is a differential +/-100 mV (200 mVpp). This means that a single-ended signal (that is, a signal that is When you measure +/- 50mV (100 mVpp). When you mention that the input to the DS25BR110 is a +-50mV open eye, is that measured single-ended (either positive input or negative input) or positive minus negative input?

    The input threshold of +/-100 mV is specified in the datasheet for differential signaling up to 3.125 Gbps. The reason why the sample pictures of the datasheet show a closed eye is because these signals are the result of intersymbol interference (ISI). ISI causes deterministic jitter as a result of a nonconsistent string of consecutive ones and zeros across media with non-trivial attenuation loss. The resulting waveform you see (i.e. the closed eye diagram) is different from how we determine the minimum input differential signal threshold.

    The minimum input threshold may be less than +/-100 mVpp depending on your operating speed. To determine the input threshold for the equalizer with regards to your application, use a clock signal operating at speed for your application and then find an input amplitude where the output from the equalizer is acceptable. It is easiest to use a 50% duty cycle clock signal (use a 325 Mbps clock or 162.5 MHz square wave) as the input and determine the minimum amplitude where the DS125BR110 can resolve a waveform that is of similar duty cycle. I recently tried sending a +/-25 mV (50 mVpp) differential signal through the DS125BR110 at 160 MHz, and the output was around 60% duty cycle compared to 51% at the input, implying that there is distortion going through the equalizer. To approach 51%, increase the input amplitude to +/- 50 mV (100 mVpp) as specified in the datasheet.

    Thanks,

    Michael

  • Hi Michael,

    thanks for your detailed response!

    The voltage (+/-50mV) is measured differentially. The single-ended values are IN+=1.275V, IN-=1.225V for a logical '1' and IN+=1.225V, IN-=1.275V for a logical '0'.

    We did some measurements with the DS25BR110 and our input signal. The output signal of the DS25BR110 was fine and it seems that its input threshold is much lower than +/-50mV. (BTW: Thanks to your outstanding sample service!)

    In order to be ready for mass production we need to ensure that the DS25BR110's input threshold will be lower than +/-50mV including variance over temperature and variance between your production lots. If we understand the datasheet correctly our input signal would violate your specification under worst case conditions.

    Your wrote “+/- 50 mV (100 mVpp) as specified in the datasheet” in the last sentence or your replay. This would be enough for our signal and maybe we did not understood the datasheet correctly. Please advise how to interpret the specified values.

    We are not using the full common mode range of the inputs but our single-ended signals are between 0.75V and 1.75V in worst case. We are also operating the DS25BR110 at about 1/10th of its max. data rate. May you give us a input threshold specification that is valid for these operating conditions and which is guaranteed for all of the DS25BR110’s production lots?

    Regards

    Manfred

  • Hi Manfred,

    Glad to hear that things are coming along!

    Hopefully I can clear up some of the confusion regarding the way that the LVDS differential input threshold is shown in the datasheet. The threshold high and low levels are at 0 mV typical. Therefore, nominally the device should switch to LVDS logic high when the input is > 0V and to LVDS logic low when the input < 0V. This is the reason for us to state that the differential threshold ((IN+) - (IN-) ) is no more than +/-100 mVpp. For example, if ((IN+) - (IN-) ) = 101 mVpp, we can ensure that this is LVDS logic level 1, whereas if ((IN+) - (IN-) ) = -101 mVpp, we can ensure that this is LVDS level 0. Production tests for this part ensure reliability of thresholds that signal character with at least +/-100 mVpp differential on the input. (Please note that this is equivalent to +/-50 mV single-ended, not +/- 50 mV differential signaling.) Below that, 100% reliability of the threshold is not ensured.

    This does not mean, however, that the device is incapable of operating at +/- 50 mV. I have spoken with some team members about these specs, and there is high confidence that the device can operate normally even with +/-25 mV single-ended (or +/- 50 mV differential), as you have observed. I believe the part should still behave correctly according to your use case (especially since input threshold typ. = 0 mV).

    We are unable to locate the exact ATE production test data used for the DS25BR110 production lots, so I unfortunately cannot offer any more insight about any new limits to use that we can back up with official test documentation.

    Thanks,

    Michael