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[ DS90UH926 ] BCC Watchdog Timer

Kenichiro
Mastermind 9165 points

[ DS90UH926 ] BCC Watchdog Timer

Hi,
According to my customer, it takes around 285ms from last SCL falling edge to SCL bus be released. Since "BCC Watchdog timer" setting is default, it's expected SCL bus to be released around 254mS. Do you have any ideas what is this approx 30ms delay? or when does UH926 start count down timer?
 
No response from UH925 side could be related to this "Out of Lock" condition which is occurred for around 130uS. We are still trying to figure out what happen on both ends, it's greatly appreciated, if you can comment on this as well.
 
Thanks,
Ken
  • 0
    TI__Genius 14015 points

    Hi Ken,

    The internal clock frequency has variation due to PVT, so the counter for this parameter will have some slop. The important thing is that they should be able to modify the register and see the affect, and get to where they need to be that way.

    Thanks,
    Jason

  • 0 in reply to Jason Blackman
    Mastermind 9165 points

    Thanks, Jason! It's clear for me.

    Regards
    Ken
  • 0 in reply to Jason Blackman
    Mastermind 9165 points

    Hi Jason,

    Let me add few more questions which are related to BCC Watchdog Timer.

    Q1:

    Where is the point that watchdog timer to start count down? I guess that should be either last clock edge or the point SDA bus be released as drawn below.

    Q2:

    Does I2C block work with CDR block? Here, what customer expects is following scenario.

    • After Ux92x sending I2C command to remote side and starting count-down of BCC Watchdog Timer.
    • Out of Lock condition happen
    • The status is reported to I2C block, thus BCC Watchdog timer being interrupted and canceled.
    • NACK condition reported to processor right away.

    As far as I check datasheet, I2C block and BCC Watchdog Timer are independent, so even if out of Lock condition happen, time count down sustain. Please correct me, if I'm wrong.

    Thanks,
    Ken