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LMH0387 SDO/SDO# Slow Fall Time

Cor Verb
Prodigy 20 points
Other Parts Discussed in Thread: LMH0387

We're using the LMH0387 interfaced to an Altera Cyclone IV FPGA and are seeing very slow fall times on the SDO and SDO# outputs, approx 10 ns from 90 to 10%. Could this be caused by a ground plane or traces beneath the package?

We missed the section in the data sheet that warns against copper under the package and have a substantial ground area and several SPI interface traces beneath the part. We're in the process of correcting our board design to remove all copper from beneath the package but want to make sure we understand why the fall times are slow before releasing the revised board design.

The data sheet warning only refers to a need for a planar surface on which to mount the package. Are there any electrical risks - of shorted nets, for example - or signal integrity risks that result from having copper under the package?

The FPGA input is configured for LVDS and the SDO signals are DC-coupled to the FPGA. The FPGA pin capacitance is spec'd at ~ 5 pF. The traces between the LMH0387 and FPGA are between 5 and 15 mm long depending on the channel (we have two channels) and are terminated in 100 ohms. Our source is an ASI generator, tested with a variety of cable lengths.

Thanks,

Cor

  • 0
    TI__Mastermind 29655 points

    Hi Cor,

    We are looking into this and will get back to you soon.

    Thanks,

    Michael

  • 0
    TI__Mastermind 29655 points

    Hi Cor,

    There are a few reasons for why a ground plane and traces beneath the package are not recommended:

    1. There may be unwanted stray capacitance on signal traces introduced due to the presence of the GND plane. TI has an applications seminar presentation affiliated with high speed board layout (SLYP173). The stray capacitance is an additional capacitor load that could be contributing to slowing down the SDO output edge.

    2. Removing copper ground or trace underneath the package creates a planar area under the laminated CSP substrate. Without this consideration, there may not be a homogeneous solder profile on the pins.

    3. A high speed trace underneath a laminated CSP can potentially cross-couple into the CSP and decrease signal integrity.

    Thanks,

    Michael

  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 20 points

    Hi,

    We have revised our PCB design to remove all top layer copper from beneath the LMH0387 package.

    This has fixed the false positive CD outputs we were getting but the SDO fall times are still slow.

    The PCB traces from the SDO outputs to the FPGA inputs are balanced and 100 ohm microstrip.

    The LMH0387 data sheet does not specify its SDO output drive characteristics and capabilities. How much load capacitance can the device drive and still meet spec? How much load capacitance could cause the SDO fall times times we're observing? (From original post: ~ 10 ns from 90 to 10%) It should be noted that our scope probe capacitance is listed as 8 pF and the FPGA pin capacitance at 5 pF.

    Thanks,

    Cor

  • 0 in reply to Cor Verb
    TI__Guru* 93670 points

    Hi Cor,

    Rise/Fall time of the output of the LMH0387 is expected to be in order of 100pS. Please note data sheet eye diagrams. Loading Cap due to the scope should be perhaps less than 1pF in order to correctly measure rise/fall time of the device. Also, i was expecting the FPGA loading Cap to be much lower as well.

    One idea is if you could get one of the LMH0387 evaluation board and check rise/fall using your setup. The device has much sharper edge rate than what you are reporting.

    Also, given this slow edge rate, is there any bit error when running DVB/ASI? 

    Regards,,nasser