pin PCLK of DS92LX2122

Hi Jung,

We have seen cases where there is a brief moment that PCLK lock is lost when the input PCLK becomes unstable or absent. At that point, the internal 25 MHz oscillator supplies the reference PCLK until the original PCLK signal returns.

It is interesting that the LOCK pin still declares that the PLL is locked. There are a few ways to perform a reset without doing a hard power-on/power-off cycle.

Option 1) Reg 0x01 [0] = Digital Reset, Retain all register values

Option 2) Reg 0x01 [1] = Digital Reset, Reset device to default register values

Can you usually communicate with the DS92LX2121 before this EMC issue occurs? Typically one device must be the slave (in this case, DS92LX2122) while the other is the remote master (DS92LX2121), so I am interested to know how you are connecting the two parts for communication. Are you using any EMI reduction techniques (for example, SSC Generation)?

If the DS92LX2122 device claims PLL lock, then it implies a valid clock signal being provided from the DS92LX2121. If you have any waveforms or scopeshots of the issue to share along with a register dump of your settings, we may be able to diagnose the problem better, assuming the two reset options I mentioned above do not help to fix the PCLK output issue.

Thanks,

Michael

Hi Michael,

Thank you for your reply.

We have tried the two reset Options you mentioned, but it does not help...

I use the SER/DES only to get the measurement data from the camera-unit. Before the EMC issue occurs, I can communicate the FPGA and the EEPROM of the camera-unit by I2C which is integrated in LVDS-Link, but not the DS92LX2121(I don't know why. I have also tried Setting Reg 0x07 [7:1] of DS92LX2122 to 0x59h).

The I2C-Bus is 100KHz and the transmitter-/receiver-LVDS clock is 12.5 MHz(PCLK).

I am not using any EMI reduction techniques by the software. The equipment work usually good and stable, only with really strong EMC-interference the Pin4 PCLK of the DS92LX2122 is always low.

Thanks.

Jun

4341.scan for TI.pdf

Hi Jung,

Thanks for the block diagram sketch. This is helpful for me to get a better picture of what is going on in the system.

You should be able to use the DS92LX2122 to communicate directly to the DS92LX2121. In order to do this, please ensure that you wake up the remote device (in this case, the DS92LX2121) and that the DS92LX2121 is made the remote master (M_S = L).

We have not exactly seen an event where CDR lock is still set while there is no PCLK output at the DS92LX2122. However, we have seen instances where the DS92LX2121 PCLK input becomes unstable, and this can cause glitches when the input clock switches from the PCLK to internal oscillator (have you disabled the internal oscillator by chance?)

Please see if the following steps are helpful:

================================================

Example I²C addresses:

SER ID = 0xB0 (7-bit address = 0.x58)

DES ID = 0xC0 (7-bit address = 0x60)

Camera ID = 0x31

===========

1)     Perform Remote Wake Up Sequence

1. Write 0xC0 to register 0x26 of device 0xC0
2. Write 0x04 to register 0x01 of device 0xC0
3. Write 0x00 to register 0x26 of device 0xC0

2)     Set the DES to Auto Ack I²C Commands

1. Write 0xED to register 0x03 of device 0xC0

3)     Program Remote Slave ID into DES Index Register

1. Write 0x31 to register 0x08 of device 0xC0

4)     Program Remote Slave ID into DES Match Register

1. Write 0x31 to register 0x10 of device 0xC0

5)     Set Ser to Ignore Input PCLK (Force to Internal Oscillator)

1. Write 0x08 to register 0x27 of device 0xB0

6)     Disable Auto Ack of DES

1. Write 0xE9 to register 0x03 of device 0xC0

7)     Program remote slave (Camera), address 0x31, registers here to optimize the pixel clock fed to the SER.

8)     Set SER to Accept the Now Stable PCLK

1. Write 0x00 to register 0x27 of device 0xB0

================================================

Thanks,

Michael