TLK10002 clocking issue

Hi,Yaoting

A reference clock is need when CDR working. PLL generate a 4 phases of half data rate clock, and CDR loop algorithm shift their phase to align to data. The final result is that it can sample the data in the most ideal position of the data.

If you directly connect the CDR output clock to reference clock input, the device cannot work for there is no right CDR clock at the beginning.   

Best Regards,

Eric

Hi Eric,

Thank you for your response!

We found if we use two same crystal oscillators both at the near and the remote sides to supply the reference clocks of two TLK10002 chips it is hard to synchronize and hard to keep data stream not being overflown. We must to sync the clocks to one in whole system transmission. Currently at remote side we use the clock from its CDR connected to an external PLL, TI's CDCM7005 as this PLL's reference clock and then use the output of 250MHz from the PLL to be the reference clock of that TLK10002's reference clock. It works. I think, indirectly, the remote side is working on the CDR clock actually. That leads me to think if i can save the PLL and directly connect the output of CDR clock to the input of the its reference clock if internally it is unrelated.

Could you help me to explain the difference between them? Why with an external PLL in between it is OK?

Thanks

Yaoting

Hi, Yaoting,

Can you tell me how the CDCM7005's two reference clock inputs(PRI_REF and SEC_REF) connected?

Whether PRI_REF connected to CDR clock and SEC_REF connected to an external oscillator?

If it is true, then i think it is reasonable.

I think at beginning TLK10002 source the clock of SEC_REF while the clock PRI_REF is not ready. And the clock is not synchronize the near side. When the CDR clock of the remote side is ready which is synchronized with near side, CDCM7005 reference clock will change to PRI_REF which is the output of CDR.

If you connected the CDR clock to the reference clock of TLK10002, it cannot work for there is no reference clock at begining.

Best Regards,

Eric

Hi Eric,

The Pri_ref is connected to CDR while a local XO output is connected to Sec_ref, but, the ref_sel is controlled by a FPGA output which is designed to be always logic "1". That means only Pri_ref has been selected all the time.

Could the PLL be while FPGA in booting phase working in Sec_ref source at beginning? If so, it can be your explanation consistently. But, usually in the booting phase of a FPGA the output logic is in high impedance. how could the PLL select one of the reference clocks? Does it has a draw-up or pull-down resistor internally?

Yaoting

Hi, Yaoting,

Firstly, you can check whether CDCM works on the automatic clock switching mode, which will disable the I/O control.

If it work on the  manual clock switch mode, you can disconnect the remote and near TLK10002, then there will be no output clock from CDR of remote side. Now you can check whether there is clock output from the CDCM, there should be no clock. You can double check when pull down the ref_sel to see anything output?

Best regards,

Eric

Thank you, Eric. I know what i should do.