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TPD12S016 in dual-link

CodeWarrior1241
Intellectual 350 points
Other Parts Discussed in Thread: DS34RT5110, TPD12S016, TPD4E05U06, TPD8S009

Hello,

I am using the DS34RT5110 HDMI retimer ina dual-link configuration, i.e. 2 of these with one feeding the diff clock to the second, ultimately presenting 6 data pairs and one clock pair to an FPGA. I'd like to use the TPD12S016 for ESD protection, and am wondering how this should be arranged...

Is it acceptable to leave the unused CLK, HPD, CEC, etc. signals of the second TPD12S016 unused?

Thanks!

  • 0
    TI__Genius 12190 points

    Hi,

    You do not need to use the CLK, HPD, CEC lines of TPD12S016. You do need to supply VCCA (for proper ESD protection) and GND, then any other pin is optional. Is there any other function of TPD12S016 you are using (i.e. 55 mA load switch)? If not, then basically you just need to provide protection for 6 3.4 Gbps data pairs and one 340 MHz clock pair. If this is the case TPD8S009 might better fit your needs. It is lower capacitance than the TPD12S016 (0.8 pF vs. 1 pF) and also offers +/- 8kV IEC61000-4-2 Contact ESD rating. For better performance, use TPD4E05U06 (< 0.5 pF) and +/- 12 kV IEC61000-4-2 Contact ESD rating.

    Regards,

  • 0 in reply to Guy Yater
    TI__Genius 12190 points

    A little more information regarding PCB layout for TPD12S016 or any TVS:

    • The optimum placement is as close to the connector as possible.
      • EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures.
      • The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector.
    • Route the protected traces as straight as possible.
    • Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible.
      • Electric fields tend to build up on corners, increasing EMI coupling.

  • 0 in reply to Guy Yater
    Intellectual 350 points

    I'm really liking some of the other features of the TPD12S016 actually. The load protection and xmit/xmit mating protection seem like really good ideas too, so I think I'll stick with this in my circuit.

    Thank you for answering my original question, this is great info!

  • 0 in reply to CodeWarrior1241
    Mastermind 9165 points
    Hello, CodeWarriro1241, Guy Yater,

    This is good information for me, too!
    Let me ask one quick question.

    My customer also does not use CEC. In this case, CEC_A and CEC_B pins cane be left open.
    Is it correct?

    Thanks,
    Ken
  • 0 in reply to Kenichiro
    TI__Expert 3500 points
    Ken-

    If your customer is not using the CEC lines, it is fine to just leave them floating! That will not cause any change to any of the other TPD12S016 functionality.

    Thanks,
    Alec
  • 0 in reply to Alec Forbes
    Mastermind 9165 points
    Alec,

    Thank you for your prompt reply!
    (Sorry, I cannot do "verify" cause it's not my original post.)

    Happy holidays!
    Thanks,
    Ken