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Could support an application scheme?

zou jason
Intellectual 280 points

Used TLK2711A as interface device.This device has synchronization interface.It is hard to deal TLK2711A reference clk.In TLK2711 datasheet, The jitter must be less than 40ps.I did not found any FPGA/CPLD/CPU has synchronization interface can meet this need.Eg.The PLL/DLL in Xilinx&Alter FPGA cause jitter .The minimum jitter is more than 100ps.

Did any can give any idea?

  • 0
    TI__Mastermind 20820 points

    Hi Jason,


    What is the specified output jitter on the Xilinx & Altera FPGA? Is it possible in your design to drive the reference clock of the TLK2711A from the same clock source that is driving the FPGA? Also, can you provide me with an idea of how the interface in your design will look? Are you using the TLK2711A as a serializer/deserializer or simply one or the other?

  • 0 in reply to Michael Peffers
    Intellectual 280 points

    In Xilinx/Altera Virtex4-7&Spartan3/6,Altera Cyclone4-5,Straix3-4 datasheet.The minimum PLL/DCM/MCM output jitter is more than 100ps.This information have been confirm by ISE and Quartus generate clock wizard.I ask their support the answer is No FPGA can export PLL/DLL/DCM clk with less than 50ps jitter.

    In my scheme,using multiple TLK2711 is my target. But right now,Using only one meet this problem.

    I want to a interface which can support the clk from 80~135MHz,Data sychornization withe the clock.It can also export tklsb&tkmsb sychornization withe the clock.It can control enable as i need.

    In a simply word, The interface of TLK2711 is similar with a sychornization SRAM(data bus and clock signal).If master device access TLK2711，how to deal with clock and data sychornization?

    As my comment,FPGA can not export the clock that can meet 2711 need.