Hello,
in my current design I'm using the SERDES chipset DS90UR905/906. During initialization all data outputs of the DES (including PLCK, HS, VS, DE) are in 3-state and pulled high/low with external resistors.
After initialization the DES outputs LOCK and PASS are going High but there are no clock signal on PCLK and all data signals are active low while the incomming data and clock on SER are correct.
What can I do to bring out the PCLK and all data?
Thanks.
Regards.
Thomas
