Other Parts Discussed in Thread: TLK10232
Hi team,
Please advise me on the following questions
Q1. Datasheet section 3.16 recommends to set up HS and LS PLL multiplier as bellow
Ref Clk (MHz) Multiplier (Ref* Multiplier) Line rate (Mbps)
HS 156.25 x 16.5 =2578.125 10312.5
LS 156.25 x 10 =1562.5 3125
On HS side, the product of Ref CLK and multiplier is quarter of HS Line rate.
On LS side, the product of Ref CLK and multiplier is half of LS line rate.
How does TLK10232 take care this multiply gap?
Q2. Please let me confirm if the definition, of VID and VIDpp in Section 9.4 and 9.6
of the datasheet, is as bellow?
As illustrated in the attached file, assuming that positive and negative of the
differential input (xxxP and xxxN) toggle with an amplitude of Vx, (measured
in single ended way), VDI is equal to Vx and VIDpp is equal to 2 times of Vx.
.
Q3. In section 9.12 of the datasheet, there is a description as bellow.
“2. Bus contention while 1.5/1.8V power is applied (>0V) must be limited to 100 hours over the projected
lifetime of the device.”
What does “bus contention” mean?
Does it mean “bus collision” (Two drivers drives same line simultaneously),
and such condition must be managed to be less than 100 hours through
entire set life?
Does bus contention occur only in MDIO interface?
Q4. In section 9.12 of the datasheet, there is a description as bellow.
“The TLK10232 LVCMOS I/O are not failsafe (i.e. cannot be driven with the I/O power disabled).
TLK10232 inputs should not be driven high until their associated power supply is active.”
Does it means that any CMOS inputs cannot be set to HGIH before the I/O
power of TLK10232 is ON?
If CMOS input is set to HIGH before I/O power is on, does it case permanent damage to the device?
If differential inputs are driven before device powers are on, does it case permanent damage to the device?
Mita