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How to reduce jitter for SDI application

Other Parts Discussed in Thread: LMH0366, LMH0394

Dear specialist

Our customer designed 80ch splitter but 5ch of them is not good jitter characteristic.
130ns required standards , but about 170ns was measured.

Jitter is getting better if input cable is reconnected after disconnected but there is case it is not rarely getting better.

In that case,if power is restart,jitter is getting better.

Although our customer assume related reclocker,could you provide any support?

Does it needs to connect DC signals between cable EQ and reclocker?

Their consideration devices is as bellow.
LMH0302SQE
LMH0366SQE
LMH0394SQE

Best regards.

  • Greetings,

    1). Could you please specify what standard is it that requires 130nS of jitter? LMH0366 is an SDI reclocker and as far as i know SDI requires much less jitter.

    2). You can DC and AC couple between the equalizer and the reclocker(LMh0366).

    3). Could you please provide your schematic for review.

    4). You mentioned 5 channels have high jitter and i assume the other 75 channels have low jitter. Is this correct?  

    Regards,,nasser

    Regards,,nasser 

  • Hi Nasser

    Thank you for your reply.

    I would like to answer about your questions as below.

    1) They are considering HD-SDI SMPTE292.

    2) Yes. They can change layout.
         If it is needed , could you provide the reason?

    3) I got their schematic.
         I would like to send you by email and something , please let me know how to send you in offline.

    4) Yes. The other 75 channels have lower jitter than 5channels.

    In addtional information , they confirm when capacitor is placed between SDO of equalizer and SDI of reclocker(LMH0366),jitter is getting better.

    best regards.

  • Hi Alpha,

    Since you said when they AC couple between the LMH0394 and the LMH0366 the jitter gets improved, in this case are they within the spec? 

    Does this improve if they provide more power supply noise filtering?

    Regards,,nasser

  • Hi Nasser

    Customer does not do AC couple but they placed capacitor like below.

    You asked whether jitter reduce if they provide more power supply noise filitering but our customer may not place noise filtering.

    Since I would like to share you their schematic,could you tell your e-mail adress.

    Best regards.

  • Yes, I have definitely resorted to the above and they work.

  • Hi

    Our customer confirmed that jitter is reduced when external crystal is removed.

    Please tell following questions?

    1. In referenceless mode,LMH0366 cannot distinguish 1.485Gbps and 1.485/1.001Gbps but is the other function same as external reference mode?

    2. Althoug they assume cause is around external clock,could you advice?

      - Crystal : ABMM-27.000MHz-B2-T ABRACON

    Best regards.

  • We got update from our customer.
    I would like to correct their phenomenon.

    They have confirmed that signal is stable if external CLK was 27MHz + 80kHz and in the referenceless mode,signal is not stable.

    They are considering using 27MHz + 80kHz.
    Are there any concern ?

    Please support about the above.

    Best regards.

  • Hi Alpha,

    There is not any concern. The external crystal is used to start up the PLL and once the device is locked it is not used any more. Here is my email address so you can send me their latest schematic for review: nasser.mohammadi@ti.com

    Regards,,nasser