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Ethernet qualification testing with DP83848YB

Michael Sch,
Intellectual 800 points
Other Parts Discussed in Thread: DP83848YB

Hey Guys,

we need to do an Ethernet qualification test of our ECU, containing the TI DP83848YB Ethernet PHY.

Our test equipment specifies a bunch of signals, the PHY needs to provide. Since we're only using the 10 MBit/s speed within our ECU, all tests will be performed at this speed. Those signals need to comply to different constraints. Here's the list of the needed signals:

  1. The transmitter should be set to generate a Pseudo Random bit pattern of at least 511 bits in duration. This type of pattern will repeat every 511 bits or more so that over a shorter measurement time, the data will appear to be random.
  2. A signal consisting of repeating sequences of preamble and SFD followed by Manchester-encoded 1s lasting for 19 ms, followed by a 9.6 us gap.

I took a look in this datasheet: http://www.ti.com.cn/cn/lit/ds/symlink/dp83848yb.pdf

I found out, that I need to configure parts of those registers:

  • CD Test and BIST Extensions Register (CDCTRL1)
  • PHY Control Register (PHYCR)
  • 10Base-T Status/Control Register (10BTSCR)

The problem is now, that the datasheet tells me nothing about the relationship between the different settings across the registers. There's also no hint on the setup sequence. The datasheet describes mainly each of the bits in one single sentence but gives no overall view of different available test modes and how to set them up.

Please provide me the information, on what I need to configure in which sequence to be able to generate the above stated test signals. Maybe it's also possible to provide a document where the test modes and their configuration are described in more detail.

Thanks in advance.

Kind regards,
Michael

  • 0
    TI__Mastermind 31600 points

    Michael,

    We will provide you this information.  Could you let us know which test equipment you are using for your Ethernet qualification?  Could you also confirm that the length of time for the Manchester encoded 1s is 19 milliseconds? 

    Patrick

  • 0 in reply to Patrick OFarrell
    Intellectual 800 points

    Hi Patrick,

    our test equipment is Teledyne LeCroy QualiPHY-ENET.

    Do you have any experience with it?

    Kind regards,
    Michael

  • 0 in reply to Patrick OFarrell
    Prodigy 10 points

    Hello Patrick,

    I´m one of the HW developer of these ECU....

    Regarding your questions:

    Could you let us know which test equipment you are using for your Ethernet qualification?

     

                    We are using the LeCroy QPHY-ENET Software.

                    QualiPHY Product Version: 7.4.0.3. (Build   199418)

                    Script Version: 7.4.0.3

                    Selected Technology: ENET

                    Configuration Setup Name: 10/100/1000BASE-T MAU Internal Dist. No T  (Copy)

                    http://teledynelecroy.com/options/productseries.aspx?mseries=252&groupid=140

     

    Could you also confirm that the length of time for the Manchester encoded 1s is 19 milliseconds?

     

                  Yes

                  --> "A signal consisting of repeating sequences of preamble and SFD followed by Manchester-encoded 1s                            lasting for 19 ms, followed by a 9.6μs gap."

    BR

    Roland

  • 0 in reply to Patrick OFarrell
    Intellectual 800 points

    Hi Patrick,

    do you have any updates regarding this topic?

    Kind regards,
    Michael

  • 0 in reply to Michael Sch,
    TI__Mastermind 18425 points

    Hello Michael,

    Generally, all the required Control registers are configured before the BIST is enabled. The following sequence of registers writes should work.

    Reg 0x00 (BMCR)             : 0x0100                Force 10Mbps operation, full duplex

    Reg 0x1A (10BTSCR)        : 0x0845                Disable jabber function, Force 10M

    Reg 0X1B (CDCTRL1)        : 0x0020                Packet BIST Continuous Mode

    Reg 0x19 (PHYCR)            : 0x0121                Disable Auto-MDIX, Enable BIST, Maintain default LED configuration and Phy address

    For the above register writes, the most common configuration is assumed. The values written in the registers can be adjusted to meet the requirement for your application.

    -Regards,

    Aniruddha

  • 0 in reply to Aniruddha Khadye
    Intellectual 800 points

    Hi Aniruddha,

    not all questions are solved from my point of view. It's still open, how the different settings in 'CD Test and BIST Extensions Register' (CDCTRL1) can be used.

    From my understanding, the behavior is somehow different, dependent on which kind of test mode is being used. What do I need to do, when I want to use any of the test patterns in CDPATTSEL?

    Kind regard,
    Michael

  • 0 in reply to Michael Sch,
    Intellectual 800 points

    Is anyone out there who's taking my questions seriously?

  • 0 in reply to Michael Sch,
    TI__Mastermind 23675 points

    Hi Michael,

    Sorry for your frustration and our delayed response. 

    I am a bit confused what you are asking for. In our datasheet we provide the listings of different test modes that the PHY can be put into depending on what register you write to and the data you write to it. Is your question how you write to the PHY to get it into the test modes or explanation of the test modes themselves? 

    Page 60 in the DP83848YB datasheet lists the CD patterns that can be used for 10Mbps mode. Page 57 in the datasheet lists the bits that need to be set to enable BIST and other Pseudo random packet generation modes.

    Regards,

    Ross

  • 0 in reply to Ross Pimentel
    Intellectual 800 points

    Hi Ross,

    thanks for your answer.

    What I'm actually looking for is the configuration of the PHY for generating all the different test patterns. The data sheet describes all the registers of the PHY and all the bits and their meaning but does not go very deep into detail.

    I'll try to figure out my questions more precise:

    • What registers/bits do I need to configure in which sequence, regardless of the used test mode (in our case for 10 MBit only)?
    • What registers/bits do I need to configure in which sequence when using one of the patterns in CDCTRL1:CDPATTSEL?
    • What registers/bits do I need to configure in which sequence when using this pseudo random data generation?
    • What's the relationship between CDCTRL1:CDPATTSEL, CDCTRL1:10MEG_PATT_GAP, CDCTRL1:CDPATTEN_10, CDCTRL1:BIST_CONT_MODE, and PHYCR:BIST_START?

    In my mind it is not sufficient to just describe the registers and the bits, without having any knowledge on how things interact.

    e.g.:
    In the description of BIST_CONT_MODE, it is stated "This can be used for transmit VOD testing. This is used in conjunction with the BIST controls in the PHYCR Register". So what? What is the conjunction? What's their relationship? What sequence is needed? Are there any limitations? Do any other configuration bits may change the behavior?

    Looking forward for answers.

    Kind regards,
    Michael

  • 0 in reply to Michael Sch,
    TI__Mastermind 23675 points

    Hi Michael,

    Just so I don't miss read your questions completely I will answer this portion below and let me know if this is what you are looking for so I can help you with the other tests: 

    e.g.:
    In the description of BIST_CONT_MODE, it is stated "This can be used for transmit VOD testing. This is used inconjunction with the BIST controls in the PHYCR Register". So what? What is the conjunction? What's their relationship? What sequence is needed? Are there any limitations? Do any other configuration bits may change the behavior?

    To do a VOD test you will set the BIST (Built-in Self Test) function on register 0x19 bit[8] to start BIST. You have the option to pick between two different BIST Sequences (PSR15 or PSR9). By default PSR9 is selected in register 0x19 Bit[10], but by writing a "1" to this bit, PSR15 can be selected. BIST_CONT_MODE in register 0x1B bit[5] will need to be set to a "1" so that the Packet generation is continuous. 10Mbps operation will not work though unless jabber is disabled. So, you will also need to disable the jabber function, which is found in register 0x1A bit[0]. Write a "1" to this bit to disable jabber.

     

    Is this what you are looking for Michael? 

    Regards,

    Ross

  • 0 in reply to Ross Pimentel
    Intellectual 800 points

    Hi Ross,

    exactly, this is the kind of detailed explanation what I would have expected. 

    Can you also please help me with the other tests?

    Just as a recommendation:
    It could be useful also for other integrators, to collect all those test execution instructions and make it part of the data sheet or to provide a separate application note for it.
    What do you think?

    Kind regards,
    Michael

  • 0 in reply to Michael Sch,
    TI__Mastermind 23675 points

    Hi Michael,

    I am glad to hear! I will provide the additional test configurations later today. 

    The team and I agree that providing an app note or section in the datasheet for qual tests would be a worthy addition. Thank you for the feedback.

    Regards,

    Ross

  • 0 in reply to Ross Pimentel
    TI__Mastermind 23675 points

    Hi Michael,

    To configure the device for the TP_IDL Mask Test, you will need to set the following:

    1. force device into 10Mbps by either straps or write a "1" to Register 0x00 bit[13]. 

    2. set the BIST (Built-in Self Test) function on register 0x19 bit[8] to start BIST.

    3. You have the option to pick between two different BIST Sequences (PSR15 or PSR9). By default PSR9 is selected in register 0x19 Bit[10], but by writing a "1" to this bit, PSR15 can be selected.

    4. BIST_CONT_MODE in register 0x1B bit[5] will need to be set to a "1" so that the Packet generation is continuous.

    5. 10Mbps operation will not work though unless jabber is disabled. So, you will also need to disable the jabber function, which is found in register 0x1A bit[0]. Write a "1" to this bit to disable jabber.

    To configure the device for link test pulse mask, you will need to set the following:

    1. force device into 10Mbps by either straps or write a "1" to Register 0x00 bit[13]. 

    ....That is all you need to do for this one.

    To configure the device for output timing jitter, you will need to set the following:

    1. force device into 10Mbps by either straps or write a "1" to Register 0x00 bit[13]. 

    2. set the BIST (Built-in Self Test) function on register 0x19 bit[8] to start BIST.

    3. You have the option to pick between two different BIST Sequences (PSR15 or PSR9). By default PSR9 is selected in register 0x19 Bit[10], but by writing a "1" to this bit, PSR15 can be selected.

    4. BIST_CONT_MODE in register 0x1B bit[5] will need to be set to a "1" so that the Packet generation is continuous.

    5. 10Mbps operation will not work though unless jabber is disabled. So, you will also need to disable the jabber function, which is found in register 0x1A bit[0]. Write a "1" to this bit to disable jabber.

    Regards,

    Ross

  • 0 in reply to Ross Pimentel
    Intellectual 800 points
    Hi Ross,

    as far as I see, there's still some information missing on how to use the different test patterns in CDCTRL1:CDPATTSEL and how other configuration bits may influence the behavior of those.

    Can you also check, what's the exact procedure for the usage of those?
    Thanks in advance.

    Regards,
    Michael

    P.S: I preferred the old forum look-and-feel much more over the updated one.
  • 0 in reply to Michael Sch,
    TI__Mastermind 23675 points
    Hi Michael,

    Here is an example since there are many options that you can play with by applying the same method.

    Lets say we want to set a pattern to have data gap set to 10us, pattern of constant manchester 1s and continuous packets sent. Here is what you will need to set in that register:

    Single write command to Register 0x1B -> 0x0033 // this sets for constant 1s, 10us gap, enabled pattern, continuous packets

    Note: you will also need to turn the jabber function off as stated in the description column of bit[5] in register 0x1B.

    To do that you will do a single write command to Register 0x1A -> 0x0001 // disables jabber

    Regards,
    Ross