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LMH0341 TRD delay

David Bleakley
Prodigy 211 points
Other Parts Discussed in Thread: LMH0341, DS32EL0124

The http://www.ti.com/lit/ds/symlink/lmh0341.pdf Revision Q datasheet shows that tRD has a typical delay of 12T.

I am aligning an system internal reference to the external SDI signal and need the most accurate delay time through the input components of my system.

I put unscrambled PAL through the lmh0341. The TRS 3FF is visible on each of the output lvds pairs (but jumps around as the lmh0341 tries to lock)


There seems to be about a 24T delay from the TRS on the input to the trs on the output when measured with an oscilloscope.

Is this an error in the datasheet, or does the device behave differently with unscrambled data.

  • 0
    TI__Guru* 93670 points

    Hi David,

    tRD of 12T is a typical value and i am afraid the device has not been characterized over different process corner and etc  to provide a precise propagation delay so we cannot guarantee a definite delay on this parameter.

    Regards,,nasser 

  • 0 in reply to Nasser Mohammadi
    Prodigy 211 points
    Hi Nasser,
    Thank you for your response.
    Is this is a logical delay rather than a process related delay as I see the 24T delay in both SD and 3G?
    At SD 270Mb/s in 27MHz DDR out.
    Each 5-bit word had an interval of T = 18.5ns
    A 24T delay at SD is 444.4ns
    At 3G 2970Mb/s in 297MHz DDR out.
    Each 5-bit word had an interval of T = 1.68ns
    A 24T delay at 3G is 40.4ns
  • 0 in reply to David Bleakley
    TI__Guru* 93670 points

    Hi David,

    Yes this is a logical delay. Each block within the device has certain clock cycle delay.

    Your Trd delay result is not what i was expecting. Could you please send us your scope shot? Also, please let me know the exact setup. I am thinking of duplicating your setup in our lab.

    Regards,,nasser

  • 0 in reply to Nasser Mohammadi
    Prodigy 211 points
    Hi Nasser,
    Thank you for your response.

    With the devices we have tested the delay looks larger than 12T in the datasheet.
    I have grabbed some screen shots from two different PCBs. I am triggering on the SAV/EAV zeros. They are inverted in my screen shots. But the code can be seen as it passes through the device.
    The 24T calculated previously may have been an error as the delay is even larger.
    At SD 270Mb/s in 27MHz DDR out.
    Each 5-bit word had an interval of T = 18.5ns
    A 24T delay at SD is 444.4ns
    We see about 598/606ns which is about a 32T delay
    LMH0341-PCB1
    LMH0341-PCB2
    At 3G 2970Mb/s in 297MHz DDR out.
    Each 5-bit word had an interval of T = 1.68ns
    A 24T delay at 3G is 40.4ns
    We see about 52/56ns which is about a 32T delay
    LMH0341-PCB1
    LMH0341-PCB2
    Please let me know what you think.
  • 0 in reply to David Bleakley
    TI__Guru* 93670 points

    Hi David,

    Actually we were expecting higher delay than what you had reported. Actually I think this is partially because the way we calculate T is a bit different from the way you are calculating this.

    Here is our calculation/expectation:

    At 270Mbps:

    f=270M/20= 13.5MHz -> T = 1/13.5MHz = 74.074nS

    Given this, we are expecting 12 X 74 + 5.5nS = 893.5nS We add 5.5nS for analog delay

    Similarly, at 2.97Gbps:

    F=2.97G/20= 148.5MHz -> T = 6.73nS

    12 X 6.73 + 5.5ns = 86.26nS

    Please note, here we call for 12 clocks but actually this could be 10 to 12 clocks. Given this, this could bring us more to the range of what you are seeing. Further please note this is a typical value and we have not characterized this parameter to call for min and max in the data sheet.

    Regards,,nasser

  • 0 in reply to Nasser Mohammadi
    Prodigy 211 points

    Hi Nasser,

    Thank you for your helpful reply. I must have misunderstood the Figure 5 in the datasheet. My understanding of Figure 5 is an output clock (RXCLK) in SD is 1/27MHz=37.03ns.

    T is half an output clock = 37.03/2 =18.5185ns. Is this a typo or am I still misunderstanding it?

    If T is calculated as you have suggested, x4 of my T, we are then only 8T delayed rather than 10-12T. Have you have you had a chance to measure the delay on a scope to see if they compare?

    Once again, thank you for your help on this issue.

  • 0 in reply to David Bleakley
    TI__Guru* 93670 points

    Hi  David,

    T is actually 1/20th of the bit rate. Please take a look at the data sheet for another device(DS32EL0124) figure 13 where propagation delay is discussed in more detail. Here is a link to this data sheet:

    http://www.ti.com/lit/ds/symlink/ds32el0124.pdf

    This parameter has been measured in the lab and please please bear in mind this is a typical value and thus we do not have a minimum or max value.

    Regards,,nasser

  • 0 in reply to Nasser Mohammadi
    Prodigy 211 points

    Hi Nasser,

    Thanks so much for your time and help with this problem.

    The ds32el0124.pdf datasheet says that the LVDS output clock period is 2T and the LVDS output bit width is T.

    This too is 5-bit LVDS. T therefore must include all 5 of the lvds bits T = 1/4 of the bit rate as 4T in SDI gives a whole pixel word.

    I have adjusted my delay calculation software and seem to be able to get the right delay on average using my understanding of the delays (24T).

    I apologise if I am still missing the obvious, but am happy to close this question, as I now have a working system.

    Thanks again

    David