Troubleshooting LV04EVK01 and LV24EVK01

Hi Kouji-San,

I think we should use the simplest setup to trouble shoot this problem before we start adding additional devices. The simplest setup that is not working is when you AC couple between DS92LV0411 and DS92LV0412. Maybe we should concentrate on this setup to make sure we understand why the receiver goes in and out of lock before we go further.

There are several potential causes that may cause the receiver to lose lock:

1). Transmit pixel clock jitter: If there is too much jitter on pixel clock this could cause excessive jitter on the output of the serializer. To rule this out, we can put scope on high persistence and note peak to peak jitter. The peak to peak jitter should be 1/10 of the bit rate. Or one can use a clean lab signal generator to generate the pixel clock.

2). Power supply noise: If the serializer supply is being driven by a switcher and there is not enough power supply filtering then may result into excessive jitter on serial output. One can either use a pi filter or use a lab supply to rule this out.

3). Make sure the same polarity on output is connected to the same polarity on input(i.e positive to positive and etc).

 4). Is it possible if you could please send us scope shot of 0411 output with RXCLKin super imposed on the output waveform? 

5). Also, if possible please send us scope picture of the RXCLKin while the scope is in infinite persistence.

Regards,,nasser

Nasser,

I apologize for the time it took to get this to you. I have attached the information you requested. I collected this data using the LV04EVK01 eval kit. It was much easier to probe than using the board I made with both the DS92LV0411/412 on the same PCB. The setup between the two should be very similar. I collected data in the two different states I mentioned in my first post. I have attached both sets of data in two separate zip files. The files in the boot screen zip file is data collected while the boot screen is shown on the display (red text over black background). The files in the video zip file were collected when the camera feed is being transmitted through the system. I took various different captures of TxClkOut to show the overall picture of what is happening to that channel

boot screen.zip

Video.zip

Greetings,

Thanks for sending us the scope shots. Looking at these scope pictures, we have some suggestions:

1). Please make sure when you are using the camera SSC is disabled? We thought TXCLK may have high jitter.

2). Please make sure CONFIG settings on both boards are the same.

3). Can you use clock only on 0411 and o412 when using the camera. The device should be able to have a steady lock.

4). While in this mode, what happens if you toggle PDB pin to re-initialize. Does it make any difference?

5). Can you please send us a picture of your setup showing different connections(for example power supply and etc).

Regards,,nasser

1) SSC0..2 are all held low

2) CFG0...1 are all held low on both boards. I noticed that the pins are marked incorrectly on the Tx EVB. The CFG pins on the Tx EVB connected to ground are marked H and the pins connected to 3.3V are marked L.

3) I have attached scope shots when using the clock only. FYI, in order to achieve this I had to disconnect the pins for the other LVDS channels and leave the only the CLK+/- pins connected. I have no other way of disabling the other lines. These scope shots are of RxClk vs TxClk, RxClk vs Lock ouptus, and TxClk vs Lock Output. Files in the boot screen zip file are when the screen is displaying the text with background status screen, the ones in the video zip are when the camera feed is active.

4)After toggling the PDB pin on both boards, I get the same results.

5)Please see attached powerpoint file for images of setup.

2260.boot screen.zip

0116.video.zip

test setup.pptx

Kouji-San,

1). In experiment #3 above, am i correct in saying the lock pin on DS92LV0412 de-serializer was in-active when you had just the clock signal connected to the RXCLKIN pin of the DS92LV0411 serializer?

2). If this is correct, in this experiment were you using the camera output clock to connect to the RXCLKIN pin of the DS92LV0411?

Please let us know.

Regards,,nasser

Hi Nasser,

1.) In the scope shots in the boot screen zip, you are looking at infinite persistence RxClk vs Lock, the signal is held high, with minimal loss of lock (the thinner dark line). In TxClk vs Lock the lock is high (yellow line) while you can see TxClk has had some loss. In the camera zip, RxClk vs Lock you see the lock signal is low for the majority of the measurement and sporadically goes high (darker blue line). And in TxClk vs Lock you see the lock is in between high and low (yellow lines) and TxClk is lost quite frequently (dark lines at bottom of scope shot).

2.) Yes I connected the output clock from our source (the clock of ds90c383) to the input clock of the DS92LV0421 (the chip that is on the eval kit but should perform the same).