[ DS90UB928 ] Delay from RIN to Valid Back Channel Communication

Kenichiro

[ DS90UB928 ] Delay from RIN to Valid Back Channel Communication

Hi,

Do you have any numbers which describe the delay in between valid RIN and achieving valid back channel communication? Please see drawing below. Is it same delay that until having valid data output (tDDLT)?

Also, is there any ways to calculate this Lock Time more accurately as per PCLK frequency? My customer would like to enable the back channel communication as soon as link is recovered.

Other reference and related discussion.

[ DS90UB928 ] Delay from RIN to TxCLKOUT/TxOUT

http://e2e.ti.com/support/interface/high_speed_interface/f/138/p/354834/1244675.aspx#1244675

Thanks,

Ken

over 10 years ago

0 Kenichiro over 10 years ago

Mastermind 9165 points

Hi,

I hope you enjoyed holiday last week.

It's greatly appreciated, if you can look into the discussion above.

Feel free to contact with me, if necessary.

Thanks,

Ken

0 Jason Blackman over 10 years ago in reply to Kenichiro

TI__Genius 14015 points

Hi Ken,

The I2C back channel communication will be available as soon as lock is established. So when Lock pin goes high, you can start sending back channel I2C commands.

The lock time is related to the PCLK frequency, but we don't disclose the internal workings of the locking mechanism. It will be longer at lower PCLK frequencies and shorter at higher PCLK frequencies.

Thanks,
Jason

Interface

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[ DS90UB928 ] Delay from RIN to Valid Back Channel Communication

[ DS90UB928 ] Delay from RIN to Valid Back Channel Communication