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XIO2001 behavior

g.f.
Guru 15520 points
Other Parts Discussed in Thread: XIO2001

Hi,

I have questions about XIO2001.

I'm using XIO2001 as PCIe-PCI bus bridge and not PCI-X.
Q1.In this case, will transaction from PCI bus be Split Transaction?

Q2.If Auto Pre-Fetch Agent is enabled, does READ be Split Transaction?

best regards,
g.f.

  • 0
    Guru 317370 points

    PCI never uses split transactions (but PCI-X supports them).

    PCI Express always uses split transactions (and they are not called that because this is the only kind of transaction).

  • 0 in reply to Clemens Ladisch
    Guru 15520 points

    Hi Clemens,

    Thanks again.

    For Q1, I uderstood that PCI never uses split transaction.
    What I want to know is, for read request from PCI to PCIe,
    will transaction from PCI bus be Split Transaction by XIO2001?

    For Q2, do you means that Read request from PCI master be Split Transaction by XIO2001
    either  Auto Pre-Fetch is enabled or not?

    best regards,
    g.f.

  • 0 in reply to g.f.
    Guru 317370 points

    On the PCI Express bus, the XIO2001 sends a read request, and later receives a separate read response.
    This would be a split transaction (except that PCI Express does not call it that).

    In PCI Express, reads always use separate request and response packets.

  • 0 in reply to Clemens Ladisch
    Guru 15520 points

    Hi Clemens,

    Thank you for the reply.
    I understood.

    Sorry, but may I ask one more question about XIO2001?

    It's about PFA_CPL_CACHE_MODE bit field of
    Pre-Fetch Agent Request Limits Register.

    I understand the difference of each PFA_CPL_CACHE_MODE value.
    But which cache are this talking about?
    What kind of situation this bit field will affect to?
    My customer want to know which configuration of PFA_CPL_CACHE_MODE
    is the best for there system.
    In their system, three PCI slot are connected to XIO2001.
    Can you please give me an advice?

    best regard,
    g.f.

  • 0 in reply to g.f.
    Guru 317370 points

    This cache is just the prefetched data.

    In "light caching" mode, prefetched data can be used only for a single burst.

    Use "full caching" mode if the PCI devices use consecutive read bursts.
    The following three registers then specify how long the cached data can be considered valid.

  • 0 in reply to Clemens Ladisch
    Guru 15520 points

    Hi Clemens,

    Thank you for the reply and the supports.

    Now I understand the light catching and full caching.
    But I can't understand the consecutive burst and single burst difference.
    What is the difference?

    Is consecutive burst means more than one data phase transfer?
    And is single burst means one data phase transfer?

    By the way, what is four packet means? Is it four read thread?

    I'm very sorry, but please give me an answer.

    best regards,
    g.f.

  • 0 in reply to g.f.
    Guru 317370 points

    A PCI read with multiple data phases is called a burst.

    Many PCI devices do not support large bursts; they terminate the burst, and then immediately start another read at the next address. To allow that other read to use data cached for the previous read, you'd need full caching mode. (But some devices do not want cached data that is too old; for example, a sound card reading from a ring buffer.)

    Reads with consecutive addresses are a thread.

    Packets are the read requests/responses on the PCI-E bus.

  • 0 in reply to Clemens Ladisch
    Guru 15520 points
    Hi Clemens,

    Thank you for the reply.

    I understood about the pre-fetch agent caching mode, finally.
    Thank you so much.

    Now, I had a following question from my customer because
    the PCI device connected to XIO2001 is selected by their end customer
    and my customer doesn't know what kind of PCI device will be connected.

    At their end customer, the burst may be single or consecutive.
    The cached data might be used at subsequent burst or might not be used.

    My customer's requirement is whatever kind of PCI device is connected,
    it's necessary to move with no problem.
    In such a case, what is the appropriate setting for "Pre-Fetch Agent Request Limits Register"?

    If they don't know what kind of PCI device will be connected,
    I guess disabling the Pre-Fetch Agent is the appropriate setting in such a case.
    ANd may be setting the value of the register to 0x0000 would be fine.
    If there are any appropriate settings, can you please give me an advise?

    best regards,
    g.f.
  • 0 in reply to g.f.
    Guru 317370 points

    In theory, the default settings should be fine.

    In another thread, you mentioned a system that locks up when under high load, except when prefetching is disabled. This is probably caused by a PCI device that uses many small reads.
    Disabling all prefetching (0x0000) always works, but would decrease the maximum possible bandwidth that other PCI devices with correct bursting could achieve. Try using less prefetching, i.e., instead of 4 x 512 bytes, use 1 x 64 bytes. Additionally, full caching mode would avoid that the same data must be fetched again for following independent read requests.
    Try 0x0180.

  • 0 in reply to Clemens Ladisch
    Guru 15520 points
    Hi Clemens,

    Thank you for the reply.

    I understood.
    So, they may disable the auto pre-fetch but should use pre-fetching(full caching/ 64bytes).

    By the way, I'm sorry but I didn't understand the <4 x 512 bytes> and <1 x 64bytes>.
    I understood that this 512byte is default value of
    PFA_REQ_LENGTH_LIMIT(Pre-Fetch Agent Request Limits register).
    But where this 4 come from? I can't find in the data sheet.

    best regards,
    g.f.
  • 0 in reply to g.f.
    Guru 317370 points
    4 is the default value of the PFA_REQ_CNT_LIMIT field.
  • 0 in reply to Clemens Ladisch
    Guru 15520 points
    Hi Clemens,

    Thank you for the answer.
    I'm so sorry for taking your time.

    So, 4 x 512 bytes means that PCI master request inital read and
    Pre-fetch agent will request 3 read requests, total 4 request.
    And each request are 512byte. Is it correct?

    Total data size will be 2048byte, so that data phase will be 512.
    Therefore, I guess the total nubmer of clocks used to complete the transfer
    will be 520 PCI cycle and the Latency Timer will be 518 PCI cycle.

    I refer to PCI specification for the Total numuber of clock and Latency Timer.
    /////////////////////////////////////////////////////////////////////
    Total Clocks = 8 + (n-1) + 1

    Latency Timer = total clocks -2
    /////////////////////////////////////////////////////////////////////

    best regards,
    g.f.
  • 0 in reply to g.f.
    Guru 317370 points
    The pre-fetch agent issues requests on the PCI-Express bus, which does not have a latency timer.
    Clocks and latency matter only on the PCI bus (when the PCI device reads the prefetched data, and it might not read all 2048 bytes in a single burst).
  • 0 in reply to Clemens Ladisch
    Guru 15520 points
    Hi Clemens,

    Thank you so much.
    I understood.

    By the way, is following part correct?
    //////////////////////////////////////////////////////////////////
    So, 4 x 512 bytes means that PCI master request inital read and
    Pre-fetch agent will request 3 read requests, total 4 request.
    And each request are 512byte.
    //////////////////////////////////////////////////////////////////

    Do you means that if configure to 4 x 512 bytes,
    Pre-fetch agent will allways prefetch 2048bytes but PCI device might not read all data?

    best regards,
    g.f.
  • 0 in reply to Clemens Ladisch
    Guru 15520 points
    Thank you so much.