DP83848C

Hi Jaime,

Could you provide a schematic? I am assuming that you used the default strap for LED_CNFG? 

Regards,

Ross

Here's the schematic. Yes I was assuming the default strap for the LED_CNFG and AN. I'm relying on the internal pullups on the LED pins. This was from an Altera reference design. With this strapping the Link LED is active high although that seems to conflict with what the datasheet states on pg 19.

0257.DP83848-schematic.docx

Hi Jaime,

After looking over your schematic it looks like you may be experiencing contention issues related to the LED_LINK pin (AN0). 

If you use the LED pins to actively drive the LEDs (Which it looks like you want from the schematic) you will need to make sure that the straps are configured properly since the pins will be configured as either active high or active low depending on strapping. I have attached two images to help in this explanation. If you want to advertise 10/100Base-T full and half duplex while having LED_LINK operate properly, you will need to have a setup similar to the one in the image below: (AN_EN = 1, AN1 = 1, AN0 = 1)

Please note: You can leave LED_ACT unconnected as you currently have in your schematic since there is an internal pull-up.

If you wish to only advertise AN0 = 0 and AN1 = 1 and AN_EN = 1 (10/100Base-T half duplex) then you will need to have LED_ACT left unconnected as you currently have in your schematic, but you will need to change LED_SPEED configuration and LED_LINK configuration as below:

As you can see, what might be occurring is a contention issue on your LED_LINK pin. 

Regards,

Ross

Thanks Ross. I did remove the LEDs so that it should rely on the internal PUs and negotiate 10/100 FDX/HDX and in reading the BMSR it is indeed doing that however the LED polarity seems to be the opposite as I described originally, unless I reset twice or go through unplugging/plugging the cable twice. Its like the LED polarity is changing but its not changing the advertised link speed/duplex because the register reads the same value for each LED polarity event.

Hi Jaime,

Forgive me if I am not understanding what you are asking correctly. From what I have seen in your schematic is this:

You have the LED_LINK going to ground where as LED_SPEED is sourced to Vcc.

For proper LED polarity configuration and operation please try and use this configuration below:

Regards,

Ross

Hi Ross,

what I was saying is that I removed the two LEDs in my schematic, effectively relying on the internal PU's and I still have the problem (contention). What I found is that in addition to the LED's on the schematic page I showed you, the Link LED signal goes to ULN2003 which we use to drive an external LED. With the ULN2003 the signal is effectively pulled down through 10.7K ohms. The symptom is that the PHY still advertises 10/100 FDX/HDX but the LED output is active LOW. I need to have the LED output be active HIGH when Link is ON. I think my solution is going to be to externally strap the pins to pull them up to 3.3V to guarantee the link speed/duplex and then drive the Link LED through the LED Direct Control Register bit 1 to force it HIGH when we read Link Status is good through the BMSR. Does that sound good?

thanks,

Jaime

Hi Jaime,

Thank you for the clarification. Yes, the internal pull-ups are weak so there might be an issue with the ULN2003 having a 10.3Kohm pull-down. I agree that you should try the solution you describe above. Please let me know what you find from doing the above procedure.

Regards,

Ross

Ross,

You're going to have to explain this one to me. I did an experiment. In addition to removing the LEDs in my schematic I added a 2.2K pull down on the Link LED output to primarily set the output polarity to active HIGH, with the side effect of strapping the AN to 110 thereby setting AN to 10/100 HDX. The polarity checked out and there is no contention, however in monitoring the MDC/MDIO traffic I can see that the PHY advertises 10/100 FDX/HDX and it successfully negotiates to 100Mb FDX. How is this possible? It is 100% repeatable 10 out of 10 resets.

thanks,

Jaime

Hi Jaime,

This is very odd behavior. A suggestion is to monitor the voltage right at the pin on AN0 (LED_LINK) before hardware reset and after hardware reset. This will allow you to see if the PHY is strapping essentially high or low. With the external pull-down it is supposed to advertise half-duplex.

Please try and monitor the pin like I said above an let me know what you find. 

Regards,

Ross

Ross,

here is a scope shot of the HW reset line (top line in screen shot) to the PHY and the LINK_LED output. As you can see AN0 is logic low approx 150mV at the time of the reset de-asserting which should cause the PHY to advertise 10/100 HDX. after a period of time and the intial negotiation you see the LINK LED output go HIGH then back LOW before returning HIGH. This short transition is due to the MAC re-initiating auto-negotiation. I'm not sure why it does this, maybe because of a time out (Its low level driver code that we don't touch). Anyway here's the proof. Let me know what you think.

6622.reset_0.tif

thanks,

Jaime

Ross,

Just wanted to add that I checked the writes to the BMCR and only bits 15 and 12 are getting set on a write (reset and AN enable) and when the BMCR is read immediately after bits 13, 12, and 8 are set. After that the BMSR is read and bits 14-11 are set along with bits 6,3,and 2. The software then does another reset and AN enable and eventually BMSR reads show that AN is complete and LINK is active. To me this means proves that software isn't forcing Link/Speed with a BMCR write and the part is doing this on its own. What do you think? By the way tomorrow is an off friday so I wont see your responses until Monday.

thanks for your help,

Jaime