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XIO2001 read performance is better than write performance

Other Parts Discussed in Thread: XIO2001

Hi Expert,

We encountered a performance problem with XIO2001 PCIe-to-PCI bridge. There is a our own designed PCI card locates at PCI bus of XIO2001.

After performed read and write access test, we got 117MB/s on read and 75MB/s on write.

Withe the same test but change PCIe-to-PCI bridge from XIO2001 to other vendor's bridge, we got 117MB/s on read and 118MB/s on write.

It seems that XIO2001 has bad throughput on write.

After searching similar problem from E2E, one answer to the throughput is to use 64Bytes for payload size.

Unfortunately, the maximum size of XIO2001 is 128B.

Is there anything we can try to improve the write throughput?

Thanks,

  • Hello,

    We have a tool that helps to configure some Registers in order to optimize the performance, this tool just tells you what value to write to these Registers.

    You can find it here http://www.ti.com/lit/zip/scpc009

    Here is a "how to" demo http://www.ti.com/lit/wmv/scpc003

    Regards
  • Hello,

    Thanks for the tool sharing. After using this performance tuning tool, only 10MB/s improvement to write access.

    But it is still not our targeted expectation. Our goal is to make read and write to be the same throughput.

    Is there any other idea?

    Can EEPROM content help on this problem?

    Regards,

  • Hello,

    It is very unlikely that you could get the same throughput with Reads and Writes. Downstream reads will always take more time to be completed, this is inherent to the PCIe-to-PCI bridge architecture(it is not related to our part).

    The Performance tuner will give you the best values based on your system.

    Regards

  • Hi

    >> Withe the same test but change PCIe-to-PCI bridge from XIO2001 to other vendor's bridge, we got 117MB/s on read and 118MB/s on write.

    And as written above in other vendor devices, it seems to have the same speed in reading and writing are out.

    >> Downstream reads will always take more time to be completed, this is inherent to the PCIe-to-PCI bridge architecture(it is not related to our part).

    So have come up with the same speed in the other device, the speed difference is not a structure, or not due to the device?

    Best regards