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TLK110 Clock XI Specification

user3893886
Prodigy 110 points
Other Parts Discussed in Thread: TLK110

Hi,

I am using TLK110 in RMII mode. I had a problem with the clock wave form  input to PHY TLK110

According this post, the clock connection between TLK110 and CPU (i.MX6) is as below in my design. External oscillator has total load capacitance up to 15pF, branch to PHY and CPU.  External oscillator is placed near PHY side

The clock wave form input to PHY is below.

It has a stop on both raising and falling edge, due to the clock signal reflection from CPU, I think.

Is there any restriction of the raising and falling edge clock on TLK110 ?

Do you have any recommend how to branch the clock signal?

Is this wave form good or not?

Best Regards

Le

  • 0
    TI__Mastermind 23675 points
    Hi Le,

    Would it be possible for you to send me the schematic and layout for this section? Let me know if you would like me to give you my email if you feel more comfortable than posting it here.

    Regards,
    Ross
  • 0 in reply to Ross Pimentel
    Prodigy 110 points
    Hi Ross
    Thank you very much for your reply.
    Can I have your email?
    Regards,
    Le
  • 0 in reply to user3893886
    TI__Mastermind 23675 points
    Hi Le,

    I looked over your schematic and layout.

    Are CX143 and R263 populated when you are seeing the hitch in the clock?

    Here is a link to a guide that might help explain best practices for layout. (http://www.ti.com.cn/cn/lit/an/snla079d/snla079d.pdf) See page #9 for external oscillator.

    The waveform is not clean, but are you seeing any packet errors when running the device?

    Regards,
    Ross
  • 0 in reply to Ross Pimentel
    Prodigy 110 points
    Hi Ross

    Thank you very much for your following my problem.

    > Are CX143 and R263 populated when you are seeing the hitch in the clock?

    CX143 and R263 were not populated in this case.


    > The waveform is not clean, but are you seeing any packet errors when running the device?

    I think there isn't any packet errors occur.
    During data transferring, signal on pin RX_ER is always low.
    After data (about 1.6GB) completed transfer, the value of RECR register is 0x00.

    I'm trying to find a suitable value of parallel termination resistor (R263) on my board. As usual, which value are you using?

    Anything else should I review my pattern or schematic?

    Best regards
    Le
  • 0 in reply to user3893886
    TI__Mastermind 23675 points

    Hi Le,

    The TLK110 EVM uses a parallel 4.7K Ohm termination. I suggest trying this value and see if there is an improvement on the clock.

    Regards,

    Ross