Hello TI,
I have a customer using the DS80PCI800 device.
They have several PCIe buses with DS80PCI800 redriver parts in them. The board he is testing now is a test fixture/development board which has a Molex iPass connector going to a pair of redrivers (one for Tx and one for Rx), and then to a Virtex 7 FPGA. The iPass connector goes to a One Stop System PCIe expansion card, which is plugged into an ITX motherboard. The interface is intended to be a PCIe Gen 3 x8 lane interface.
So far, they have been able to get the Xilinx part to enumerate when we have tried PCIe gen 1 x8 and PCIe Gen2 x8, but they have not been able to get PCIe Gen 3 x8 to work.
They think the problem is related to the settings of the redriver part, and that this is causing the PCIe gen 3 negotiation sequence to not work properly. They say this because they have a Xilinx load which attempts to bring enumerate as a PCIe Gen 3 x1 lane interface. This has been working , but they cannot get PCIe Gen 3 x8 to work.
On other E2E posts we see comments that users should try different EQ and level settings to see what works best if the standard setting do not work.
I’m wondering if there is any software tool for aiding in doing this, or if there might be more documentation on some of the register bits undefined in the datasheet.
At this point, they have to generate a new eeprom bit file manually for each setting I want to try, and this is taking a long time.
One more thing I should note – we tried connecting two Xilinx parts to each other using the same Test Fixture/Development board. We have been able to run ibert link tests error free at 5Gbps and 10Gbps on all 16 lanes (8 Tx and 8 Rx) in this configuration. This gives me confidence that the pcb layout is functional and that we will be able to get the links working properly at PCIe Gen 3 x8 lanes. I really think it is just a matter of bit settings.
Any help would be appreciated.
Summary:
Using DS80PCI800 redriver parts for an 8 lane PCIe interface.
We can establish links through the parts at PCIe Gen 1 x8 and PCIe Gen 2 x8
We can establish a link at PCIe Gen 3 x1 lane through the parts.
We have tried running Xilinx ibert tests on the links and have run error free on all lanes at both 5Gbps and 10Gbps.
We think the problem is related to the DS80PCI800 eeprom settings.
I am looking for a software tool or other documentation to help speed up the process of trying different eeprom settings.
Thanks,
Dan
