Hi Elias, Thank you for the insightful responses through all of these threads pertaining to the TUSB1310A.
For anyone that can help me, I have a board that we are designing with an FPGA (Xilinx Kintex 7) connected to the TUSB1310A. The idea is to have the FPGA implement the LLC functionality, but (due to my naivete and lack of experience) I am confused about a major piece of this configuration. My specific questions are listed below:
- Do I have to write the Verilog/VHDL code myself to implement this LLC or is there some place that has already done this that I can use?
- Is it accurate to assume that this LLC has the code that communicates to the PIPE interface? Or is the PIPE interface a different block of code that I need to add to the FPGA via some other core?
- Can you send me a reference schematic using the TUSB1310A and an FPGA chip?
- Along with a reference schematic, is there any documentation that can give me a high level understanding of what's involved after the board design, to get USB SuperSpeed to work at full bandwidth (with dummy data)? In other words, is there any documentation regarding what's involved to program the FPGA, etc, that would get me up and running to test the interface?