TFP401 timing issue phenomenon

Hello Takahashi-san,

I would like to know more about the issue because this could be just an artifact of the lab equipment.

Can you describe what is the failure they are having at system level?
I have some questions/comments regarding the above descriptions:

1) Issue#1, this could be an artifact of the scope. Where are they measuring this? at the TFP401's pin? Have they changed the scope to trigger falling edge? Is the DVI input to the TFP401 encoded with falling edge at the video source?

2) Issue#2, a cross-talk issue is not caused by the Device, they should have some reflections due to poor layout design, is this cross-talk causing system level failures? Can you get the schematic and layout for review?

3) For Issue#3 and Issue#4, the scope captures does not make sense with the numbers they are provided, for example, if the ODCK=162MHz then the Period would be equal to 6.17ns, so a setup time of 6.53ns will cause BA0 to be before the complete clock cycle in the above scope capture, however, the scope capture is representing a setup time around 3ns.
Kind the same goes for Issue#4, so please ask customer to double-check that.

For your reference I am measuring a 2.2ns setup time with a clock freq=165MHz

Regards