Quotation from a DS90CR287 datasheet:
"The transmitter input clock may be applied prior to powering up and enabling the transmitter. The transmitter
input clock may also be applied after power up; however, the use of the PWR DOWN pin is required. Do not
power up and enable (PWR DOWN = HIGH) the transmitter without a valid clock signal applied to the TxCLK IN
pin."
In my application the DS90CR287 is "fed" by a FPGA circuit.
The FPGA would start, after the code has been loaded, as follows:
1) 'PWR DOWN' is driven low (i.e. Power Down mode is entered)
2) Valid clock signal starts on TxCLK IN
'3) PWR DOWN' is driven HIGH (i.e. Power Down mode is abandonned).
Because of "the physics" of the FPGA, the 'PWR DOWN' will be HIGH until the FPGA code is loaded and the FPGA starts. So there will be a HIGH 'PWR DOWN' at some time "long" before a valid clock appears on 'TxCLK IN'. But 'PWR DOWN' is low when the clock applies, driven HIGH after clock is applied.
Will this work?
/Staffan Cronstrom
