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DP83865 PHY autonegatiation @ 1000Mbps issue

Vineetha Thomas
Prodigy 140 points
Other Parts Discussed in Thread: DP83865

Hi TI support,

In my board I use the Gigabit PHY dp83865. Following is the description of the problem I face.

When I configure the PHY dp83865 in my board for auto-negotiating (it is advertising 10/100/1000 capability), and connecting it to another board (the same kind board, with the same configurations ), it successfully completes auto-negotiation to 1000Mbps and link is established.

When I connect the same board to a Gigabit switch (D-link DGS-1008A), having configured the board to Auto-negotiation (advertising 10/100/1000 capability), it fails to complete auto-negotiation (the AN complete bit (#5) in Basic mode status register (0x01) is never set) and the link is not established.

Interestingly, if I connect the same board with exactly same configuration to another Gigabit switch (GS608 netgear) , the PHY auto-negotiates to 100Mbps, and the link is established. One would expect it to auto-negotiate to 1000Mbps, as the switch supports the speed.

In another trial, when I connect the board directly to a PC, again it fails to complete auto-negotiation and link is not established.

In short, at my end, it seems the PHY is able to complete auto-negotiation @1000Mbps only with the same PHY, and fails to do so with other Gigabit PHYs. Since this will then be a great limitation for us, can you help confirm if this is a PHY configuration issue or could this be some kind of compliance issue? Please note that I have already gone through the FAQ section in the PHY datasheet and the workaround suggested in the FAQ 7.15 has already been tried, with no results. Is there some other PHY configuration that has to be taken care of here?

Thanks,

Vineetha

  • 0
    TI__Mastermind 31600 points
    Vineetha,

    Could you provide the register configuration of the PHY when connected to the D-link DGS-1008A switch and attempting to link? Please read the registers multiple times and provide the results of each read. The status of some bits is latched and I would like to see the final values of the bits.

    Patrick
  • 0 in reply to Patrick OFarrell
    Prodigy 140 points
    Hi Patrick,

    Thanks for your reply. I have posted below the register reads in two cases.
    1. Our board (with dp83865 PHY) connected directly to PC
    Here I see that the PHY autonegotiates to 100Mbps (and not 1000 Mbps, note that PC supports 1000Mbps)

    2. Our board connected to switch DGS-1008AOur board connected to switch DGS-1008A


    Case1: Our board (with dp83865 PHY) connected directly to PC
    Register Dump 1:
    bmcr - 0x1140
    bmsr -0x7949
    Anar - 0x5E1
    anlpar - 0xC1E1
    _1ktcr - 0x300
    _1kstsr -0x0
    _1kcsr - 0x3000
    strap_reg - 0xC041
    link_an - 0x418

    Register Dump 2:
    bmcr - 0x1140
    bmsr -0x796D
    Anar - 0x5E1
    anlpar - 0xC1E1
    _1ktcr - 0x300
    _1kstsr -0x0
    _1kcsr - 0x3000
    strap_reg - 0xC041
    link_an - 0x40E


    You will see from link_an register that AN is complete but it auto-negotiated to 100Mbps.

    Case2: Our board connected to switch DGS-1008A
    Register Dump 1:
    bmcr - 0x1140
    bmsr -0x7949
    Anar - 0x5E1
    anlpar - 0xC5E1
    _1ktcr - 0x300
    _1kstsr -0x0
    _1kcsr - 0x3000
    strap_reg - 0xC041
    link_an - 0x418

    Register Dump2:
    bmcr - 0x1140
    bmsr -0x7949
    Anar - 0x5E1
    anlpar - 0xC5E1
    _1ktcr - 0x300
    _1kstsr -0x0
    _1kcsr - 0x3000
    strap_reg - 0xC041
    link_an - 0x418

    Here you will note that AN was not even completed. If I poll for the AN complete bit in BMSR register, it does not come out of the polling loop as the bit is never set.

    Please look into this to see what could be the issue.

    Thanks,
    Vineetha
  • 0 in reply to Vineetha Thomas
    Prodigy 140 points
    Hi Patrick,

    Do you have any comments w.r.t the observations in my reply above.

    In this same context, I have another clarification.

    In our board, the pin #94 of the PHY (MULTI_EN_STRAP) is left floating. This pin decides multi-node enable option. However, I see from the datasheet of the PHY that this pin has an internal pull down. Does it then mean that the value strapped for this pin at reset is 0 and it selects single node priority option? Do you think this could be an issue? Kindly provide your comments.

    Also, in the register values shared above, you will see that _1kstsr (1000Base-T status register) is all zeroes. Is this expected?

    Thanks,
    Vineetha
  • 0 in reply to Vineetha Thomas
    Prodigy 140 points

    Hi,

    Could someone please help me with the questions above?

    Vineetha

  • 0 in reply to Vineetha Thomas
    TI__Mastermind 23675 points
    Hi Vineetha,

    Have you tried forcing the PHY into 1000Mbps? Can you establish link in forced modes?

    Pin #94 should not be an issue. Since this pin is left floating, Auto-neg will take care of figuring out master/slave.

    Regards,
    Ross
  • 0 in reply to Ross Pimentel
    Prodigy 140 points

    Hi Ross,

    I did try forced mode for the dp83865PHY in both connecting to 1Gbps switch and also directly to the PC. It failed to establish link in both cases. But I saw these pointers in the PHY datasheet that explains this behavior.

    1. dp83865 --> 1Gbps switch (with dp83865 PHY forced to 1000Mbps)

    Failed to establish link

    Note from PHY datasheet, FAQ section 7.7 :However, for 1000 Mbps operation this parallel detection mechanism is not defined. Instead, any 1000BASE-T PHY
    can establish 1000 Mbps operation with a link partner in the following two cases:
    — When both PHYs are Auto-Negotiating,
    — When both PHYs are forced 1000 Mbps. Note that one of the PHYs is manually configured as MASTER and the other is manually configured as SLAVE.

    Note from PHY datasheet, section 3.2 : It should be noted that manual 1000BASE-T mode is not supported by IEEE. The DP83865, when in manual 1000BASE-T mode, only communicates with another National PHY. The manual 1000BASE-T mode is designed for test purposes only.


    Hence it seems to be expected that if the PHY is configured for forced mode in connecting to a switch(which is autonegotiating) the link will not be established. Please note that I have tried all combinations for Master/Slave selection - auto M/S select, force the PHY to Master, Force the PHY to slave.

    2. dp83865 --> PC(with dp83865 PHY forced to 1000Mbps)

    Here, I tried with Auto-negotiation enabled at PC, and also with PC forced to 1000Mbps. I tried with both straight cable(with MDIX enabled) and cross-over cable. Link failed to establish. But from the notes in the datasheet mentioned above, it seems the failure is expected- Please comment on this.

    Hence it seems to me that forcing the PHY to 1000Mbps when connecting to any switch or PC is an INVALID test case. The only way the PHY can establish link at 1000Mbps seems to be through auto-negotiation - which is failing. Please comment on this. Please note that auto-negotiation works for us at 10/100 Mbps speeds with switch/PC. Also auto-negotiation works between two dp83865 PHYs at 10/100/1000Mbps.

    I also tried probing the link pulses, following the procedure detailed in "AN-1329 DP83865 and DP83864 Gigabit Physical Layer Device Trouble Shooting Guide", section 3.3. I could see the link pulses in the failure cases also (failure implies auto-negotiation fails to complete) - So is the Link pulse not an indication of successful auto-negotiation?

    In this context, please help me with the following specific clarifications.

    1. Any ideas on how to debug auto-negotiation issues would be helpful. What signals to probe at the PHY end to see what causes the failure? Are there any status bits indicating the same?

    2. Is there any register/bit that indicate what caused the auto-negotiation to fail ?

    3. Could you provide me with the mailing address for your private support, so that we could send over our schematic for the PHY connections so that you could verify it?

    4. Is there any reference schematic available for the PHY? Are there drivers available?

    5. Can you confirm if there has been any issues reported regarding auto-negotiation at 1000Mbps.

    6. If you could provide a checklist for important sw/hw settings to be taken care of for 1000Mbps, it would be useful.

    7. Any other relevant comments on the issue?

    Thanks,

    Vineetha

  • 0 in reply to Vineetha Thomas
    Prodigy 140 points
    Hi TI Support,

    Could somebody please comment on the query above?

    Specifically, I wanted to bring to notice one register read (posted in a thread above). The LINK_AN reads 0x418 => the speed status [4:3] is 2'b11 => mentioned as reserved in the PHY datasheet.

    Thanks,
    Vineetha
  • 0 in reply to Vineetha Thomas
    TI__Mastermind 31600 points

    Vineetha,

    I apologize for my delay in helping close this out.

    If you will email me the schematic, we will review it. My email address is <email address removed>.

    I don't have any experience with the DGS-1008 switch, but I notice that it has a feature to adjust the power supplied to a port according to the length of the connected Ethernet cable. Have you tested with different cable lengths? I would be interested to know if you see different results for short and long cables.

    Could you also provide the configuration for the Auxiliary Control Register (AUX_CTRL), register address 0x12?

    Thanks,
    Patrick

  • 0 in reply to Patrick OFarrell
    TI__Mastermind 27743 points

    Hello Vineetha, Hello Patrick,

    Wondering if their was any root cause fort the above mentioned issue. We are seeing similar behavior on some of our internal ref. design boards. 

    Please let me know if there is any workaround available. Thanks.

  • 0 in reply to Prasad Jondhale
    Prodigy 30 points
    Hello Vineetha , Patrick and Prasad,

    I am facing same issue. This issue exist in around 10% of the boards what we've produced.
    I could see IEEE waveform identicle for passed (Gigabit Link success) and failed (Gigabit Link failed) board.
    I've checked soldering quality and other HW aspects as well.

    One question whether 25MHz oscillator/crystal can cause this issue. I don't think so but just to make sure if my understanding correct.

    Please let me know if you guys found any solution or workaround.

    Thanks & Regards,
    Anuj
  • 0 in reply to Anuj Singhvi20
    TI__Mastermind 27743 points
    Hello Anuj,

    For me issue is still pending. Waiting for PHY team to reply.
  • 0 in reply to Prasad Jondhale
    TI__Mastermind 19780 points
    Hi Prasad and Anuj,

    We are still investigating the auto-negotiation of the DP83865.

    Thanks,
  • 0 in reply to Rob Rodrigues
    Prodigy 30 points

    Hello Rob,

    Please let me know if you get any hint regarding DP83865 auto negotiation issue @ 1000Mbps .

    Thanks & Regards,

    Anuj

  • 0 in reply to Anuj Singhvi20
    Prodigy 30 points
    Hi Rob,

    We are still in the same situation.
    Did you get anything for me regarding autonegotiation issue?
    It is going to be difficult to wait for longer time due to customer's pressure.
    Please let me know if you have any outcome for this issue.

    Thanks & Regards,
    Anuj
  • 0 in reply to Rob Rodrigues
    Prodigy 10 points
    Hi Rob,
    We are extremely interested in your findings. I've been working on the issue that Anuj Singhvi and Kevin Gagne have posted about. Recently, we built a batch of 100 boards that has the DP83865 on it. Of the 100 boards, 17 failed our GigE diagnostic test. I had the DP83865 replaced on the 17 failed boards. 14 of them then passed our GigE diagnostic test. I then had the DP83865 replaced again of the 3 remaining failed boards. They now pass our GigE diagnostic test. This is leading us to believe that we are receiving parts from TI that are DOA. Please let us know what you think of this latest development regarding this issue. If you need to refresh your memory of this issue, please refer to the posts submitted by Anuj & Kevin. Thanks.

    Geoff
  • 0 in reply to Geoffrey James
    Prodigy 10 points
    Hi Rob,

    We have been working on the GigE issues associated with this product for over a year and are still having issues as Geoff has described above. We have this Phy on 4 evaluation boards and MUST resolve this FAST, so are looking for solid support. If we can't resolve this issue in the next few weeks, i think we will end up cutting our losses and remove the DP83865 from 4 products.

    At this point, I'd like to arrange a meeting with the Product manager of the DP83865 product for this Friday 4/14/17 1:00 pm east coast time? Can you help set this up please?

    Regards,
    Joe Bastos
    Analog Devices Inc.
    Hardware and Firmware Manager
    2 Elizabeth Drive
    Chelmsford Ma 01824
    Office: 978-268-3394
    Cell: 603-234-4102