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Deserializing a DDR signal

Jacob Putz
Intellectual 665 points
Other Parts Discussed in Thread: ADS62P29

I am designing a system around the ADS62P29. The outputs of the ADC essentially have a DDR LVDS setup in which when the clock is high Dn is output on the pins and when the clock is low, Dn+1 is output. What component would be best to separate out the Dn and Dn+1 values of the signal?
  • 0
    TI__Genius 13475 points
    This should be a simple enough thing to integrate into whatever you are using to process the data - an FPGA? - if I were to do it with discrete logic, I would latch the word with one falling edge of the CLK, then latch the entire word (both the ADS62P9 and the latch output) when the CLK is high.