Hi,
I am not able to see any packets received on a pc connected to the DP83865 part. I have tested the transmitter BIST and the phy can transmit correctly since I see the bist packets in wireshark.
Before I start looking at timing of the data/clk lines going to the phy, I want to be sure that the packet I am transmitting has the correct FCS. I would appreciate any help in confirming this.
I used the easics crc generator (CRC32 - Ethernet/AAL5) to create the CRC computation function.
I then did the following to create the FCS (output_crc is the fcs and crc_reg is from the crc from the easics function):
ouput_crc(31 downto 24) <= NOT crc_reg(24 to 31);
ouput_crc(23 downto 16) <= NOT crc_reg(16 to 23);
ouput_crc(15 downto 8) <= NOT crc_reg(8 to 15);
ouput_crc(7 downto 0) <= NOT crc_reg(0 to 7);
The fcs was then appended to my frame last significant Byte first
I simulated doing a loopback on the packet I sent and fed all the bytes (minus preamble and start byte) to the easics crc function again and the crc at the end of packet was "0xC704DD7B" which is the CRC32 residue from a packet transmitted with the correct FCS as indicated on the frame check sequence wiki.
So can I assume that my packet is correct at this point and I should be looking at signal integrity between fpga and phy.
The whole packet minus preamble and start byte including fcs is below for good measure:
(X"ff",X"ff",X"ff",X"ff",X"ff",X"ff",X"4d",X"4b",
X"53",X"49",X"4e",X"53",X"08",X"00",X"45",X"00",
X"00",X"38",X"00",X"00",X"40",X"00",X"80",X"11",
X"51",X"16",X"54",X"52",X"55",X"4d",X"ff",X"ff",
X"ff",X"ff",X"C5",X"4e",X"C4",X"53",X"00",X"24",
X"00",X"00",X"34",X"12",X"00",X"00",X"78",X"56",
X"ab",X"90",X"39",X"fb",X"ad",X"fd",X"dc",X"fe",
X"ef",X"cd",X"55",X"55",X"05",X"00",X"12",X"80",
X"49",X"23",X"10",X"00",X"00",X"80",X"0c",X"59",
X"64",X"5e")
Thanks for the help,
Amish
