HD3ss6126 schematic review

Nanfang Liao

Intellectual 2085 points

Other Parts Discussed in Thread: HD3SS6126

One customer uses our HD3ss6126 as USB2.0 and USB3.0 1 to 2 switch application . The input is J1101 that is a connector. SW01, SW02 is 1.8V GPIO and power supply of HD3ss6126 is 3.3V.

1. Please help to check if the schamtic is right?

2. Because customer connect HD3ss6126 to external connector J1101, they put some ESD device(D114、RV1103、RV1104) before HD3SS6126, these ESD devices will impact the channle SI performace, so the SI performace is OK? Can the customer connect the J1101 to HD3SS6126 directly that don't use ESD device?

Regards,

Nanfang

over 9 years ago

0 C. Ryan Land over 9 years ago

TI__Genius 9860 points

Moving to Consumer and Computing forum for support.

0 Elias Villegas M. over 9 years ago

TI__Guru* 76130 points

Hello,

By hard-wiring SEL you will be unable to switch from one downstream to another, i.e. according to your schematic the SSA will be always output to the SSC and never to the SSB lines.
In addition, connecting HS_OE# high will disable the USB2.0 portion.

You can find a reference design here www.ti.com/.../slau541.pdf
Regards

0 Nanfang Liao over 9 years ago in reply to Elias Villegas M.

TI__Intellectual 2085 points

Thanks for your comment. Can you give more detail comments about my three questions? thanks

Regards,

Nanfang

0 Elias Villegas M. over 9 years ago in reply to Nanfang Liao

TI__Guru* 76130 points

Hello,
You are right that adding ESD clamps will affect the signal integrity.
I can't tell you whether they have to use them or not, it all depends on their system requirements and characteristics, I can only tell you that the ESD protection is optional.
For example, our EVM does not use ESD protection and it works just fine.

Regards

Interface

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HD3ss6126 schematic review