Hi,
I'm planning on building a 10gbit Ethernet system using a Xilinx Artix-7 FPGA which has 16 6.6 Gbps SERDES. These aren't fast enough to drive a SFP+ directly but more than adequate for XAUI, so I figured I could use a TLK10232 to turn two channels of XAUI (8 SERDES) into two SFP+ interfaces.
Then something occurred to me... this is a waste of bandwidth since the SERDES would be running at about 3 Gbps vs the 6 they're capable of. If there was a way to run the TLK10232 in 2:1 10gbps mode, such that two 5gbps inputs produced one 64b66b encoded 10gbps output, this would allow me to use half as many transceiver channels on the FPGA.
Preliminary reading of the datasheet doesn't seem to suggest this feature exists. It seems possible to do 4x 8b10b to 1x 64b66b, 2x 8b10b to 1x 8b10b, but not 2x (any line code) to 64b66b. Am I correct in that this is impossible, and I'm stuck using XAUI and four FPGA transceivers per SFP+, or am I missing something?
