We are looking to pass the HDMI compliance testing and we have questions/issues on the DDC/CEC capacitance testing from section 7-13 while using the TPD12S016 EVM dev kit. We have are using a custom SOC that has the HDMI A side interface to the TPD12S016. How do we tie the LS_OE and CT_HPD pins since our SOC doesnt have any GPIO that would control these?
It appears LS_OE would get tied to the A side Hotplug detect line do we just tie the CT_HPD line high to fully enable the part at all times?
If this is the case on the TPD12S016 EVM kit I assume to test this we supply +5V to the 5V supply pin and VCCA would be the A side voltage which our SOC supplies which is +3.3V. We then leave the LS_OE On and CT_HPD On on the eval board. But if we do this with both a 5V and 3.3V power supply on and take a measurement with a HIOKI 3522-50 the DDC lines read about 2.6nF which fails the section 7-13 spec of >50pF. If you set the CT_HPD to Off then the measurement is around 20pF which would pass the test.
The overall question would be if our custom SOC having only the A side HPD pin can we really control and set the TPD12S016 into a mode where it would pass the section 7-13 DDC/CEC capactiance test both powered on and off?