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D92LV18 routing of DINs/ROUTs

savino giusto
Prodigy 180 points
Other Parts Discussed in Thread: DS92LV18, SCAN921821, LVDS-18B-EVK

I'm designing a board for optical transmission of low frequency signals using a pair of DS92LV18.

As I'm in prototyping phase, I have been able to get the SerDes working with common gigabit optical transceivers (SFP) and to extablish a link.

My concerns are about the PCB layout tracks that lead to DIN and ROUT pins of the DS92LV18.

This picture is taken from the 18-bit SerDes evaluation kit user manual (snlu11). It looks like the designer here tried to use tracks of the same lenght when routing DINs and ROUTs. Is this required for the SerDes to work correctly?

I'm asking this because in my prototype some lines are not working, and it appears that those lines are the ones who are making a tortuous path.

Thank you in advance for you answer

Savino Giusto,

Eletech s.r.l.

  • 0
    Prodigy 180 points

    Maybe i didn't write it clear enough:

     I'm asking if this kind of routing is needed for the SerDes to work correctly.

  • 0 in reply to savino giusto
    TI__Guru* 93670 points
    Greetings,

    As you noted, this was done to make sure trace lengths, on DIN and ROUT, are the same. This ensures close to 50% duty cycle. Else we could introduce Duty Cycle Distortion(DCD). DCD is another type of jitter and degrades signal integrity of the differential pairs.

    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    Prodigy 180 points

    Hello Nasser,
    Thank you for your answer. I noted that kind of routing and i'm aware that it is used when it's needed to have traces of the same lenght. But DIN and ROUT aren't differential pair nor do they drive high frequency signals, in my specific application.
    Another thing i noticed is that in the evaluation board all the DIN inputs are terminated with 50ohm resistors. WHY?

    Regards, Savino

  • 0 in reply to savino giusto
    TI__Mastermind 29655 points
    Hi Savino,

    Although the DIN and ROUT signals are LVCMOS/LVTTL, it is still important for them to align well with the respective clock signal so that they can be serialized on the correct clock cycle during LVDS data transmission.

    The DIN inputs you are referring to correspond to the SCAN921821 part. However, the DS92LV18 has a similar input structure. The LVCMOS inputs are designed with an internal default pull-down resistor (~200 kOhm). I believe the use of the external 50-ohm resistors is simply to provide a stronger pull-down resistance to GND if the pin is left unused. Otherwise, you should be able to operate the DS92LV18 or SCAN921821 part without those pull-down termination resistors populated on DIN.

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    TI__Expert 3050 points
    Hi all,

    Just to clarify, the traces are routed to be phase matched. This means the propagation time between all of the DIN traces and all of the ROUT traces have the same electrical flight time. This is done to maintain the propper setup and hold timing for the clock strobe.

    On average, FR-4 has a propagation delay of 150 - 180 ps per inch of trace. It is often times not necessary to perfectly phase match all of the traces in a bus, but it is important to keep in mind the setup and hold timing requirements as stated in the datasheet.

    Mike Wolfe
    DPS APPS / SVA
  • 0 in reply to Mike Wolfe
    Prodigy 180 points

    Hi all,
    Thank you very much for your answers.
    I took into consideration setup and hold requirements, but as long as my design involves low frequency signals on DIN/ROUT pins, I didn't worried a lot about delays whose order of magnitude is ns.

    My prototype is working both in TX and in RX sides. The serdes is locking correctly and I succeded in trasmitting signals between two boards and accross the same board (over fiber). The only DINs and ROUTs that aren't working are the ones whose traces are a little more "messed up". These tracks have vias in their path and cover a much longer distance than others.

    I added a picture of the routing as I made it on the prototype to make clear about which signals are not working.

    Regards, Savino.

  • 0 in reply to savino giusto
    TI__Expert 3050 points

    Hi Savino,

    Can you provide a scope shot of the these signals. It would be good to have a scope shot of the clock as a reference point.

    Also as a general recommendation, when you use vias for controlled impedance lines it is important to make sure that there is a nearby via that provides a constant ground reference for the signal via. These vias are typically called return vias, since they provide a path fort he return current for the signal.

    Also, can you describe which layers you use for these signals and how many layers there are in your pcb stack up?

    Mike Wolfe

    DPS APPS / SVA

  • 0 in reply to Mike Wolfe
    Prodigy 180 points

    Hi Mike,

    Thank you very much for your help, i really appreciate.

    I uploaded the scope shots of the signals. I used DIN5/ROUT5 with a 3.9KHz signal. The DIN/ROUT couples which have a different lenght in routing always show a high level on ROUT, ignoring whichever signal i put on DIN.

    I know about return vias but i wasn't aware that DIN/ROUT lines where controlled impedance lines. As long as i use them with low frequency signals they should work regardless of their lenghts.


    My board is 4 layer stacked as follows:

    TOP signal routing

    GND plane

    VDD plane

    BOTTOM signal routing

    The routing of DIN/ROUT goes along top and bottom layer. Now that you mention it looks to me clearer than ever. If those lines are controlled impedance the VDD plane just under the bottom signal routing layer may be the guilty one. As it wouldn't guarantee the return path for impedance.

    The only thing that sound strange to me is the reason why my prototype doesn't work with low frequency signals either.


    Regards, Savino

  • 0 in reply to savino giusto
    TI__Expert 3050 points
    Hi Savino,

    Do you have added filtering on the clock line? The clock signal appears to be degraded a bit.

    Also, can you clarify what you mean by "doesn't work at low frequency signals either"?


    Mike Wolfe
    DPS APPS / SVA
  • 0 in reply to Mike Wolfe
    Prodigy 180 points

    Hi Mike,

    I dind't add any filter on the clock line. I used a CDCE913PW with a 27MHz crystal. Maybe the clock signal appears to be degraded a bit because i don't have a fast enough scope?

    When i say "doesn't work at low frequency signals either" i mean that if the problem was caused by a impedance mismatch it would have worked at least with low frequency signals (such as the 4KHz i used in my tests).

    Regards, Savino

  • 0 in reply to savino giusto
    TI__Expert 3050 points
    Hi Savino,

    If the clock comes from a CDCE913PW , how is it synchronized with the data? Have you confirmed the setup and hold times are within spec?

    For the low frequency issue, I am interested in what you mean by not working. Can you provide a detailed description of what you see happening? Does any data come out of the device? Do these bits output any meaningful data or it is junk data? How do the signals look?


    Mike Wolfe
    DPS APPS / SVA
  • 0 in reply to Mike Wolfe
    TI__Expert 3050 points
    Hi Savino,

    Also, please confirm that the data input for your low frequency is 4kHz and the clock is still in the 15-66 MHz range. Thanks.

    Mike Wolfe
    DPS APPS / SVA
  • 0 in reply to Mike Wolfe
    Prodigy 180 points
    Hi Mike,
    Sorry for the late answer but I haven't been in my office since last month.
    I can confirm you that setup and hold times for DINs are within spec. The clock that comes from a CDCE913PW is 27MHz.
    Here a more detailed description of what I see happening:
    I turn on my prototipe boards and i see them sync since the lock signal goes low (I can see the LED light).
    From this point on I can put whatever signal I want on the DIN4~DIN16. The corresponding outputs on the other board (ROUT4~ROUT16) work just fine (I can recognize the exact sequence i put on DINs).
    However ROUT0~ROUT3 are appearently dead. It doesn't matter what i put on DIN0~DIN3, these outputs will remain at a high state.

    I hope I made myself clearer this time, I really appreciate your help.
    Thank you very much.

    Savino Giusto
  • 0 in reply to savino giusto
    TI__Expert 3050 points
    Hi Savino,


    Can you send some pictures of your system?

    It would be helpful to have some scope shots of the clock and data signals on the DIN pins.

    Also, can you share a schematic or pcb layout file of your board? It might be good to do a visual inspection of the DS92LV18 to make sure there are not assembly (solder) issues.

    Mike Wolfe
    DPS APPS / SVA
  • 0 in reply to Mike Wolfe
    Prodigy 180 points

    Hi Mike,

    Inside this archive you can find all the shots and the pictures you asked me.

    If you need, I can send you actual design files. They are orcad files.

    Thank you

    Savino

  • 0 in reply to savino giusto
    Prodigy 180 points

    I was wandering if it was possible to have the layout files from LVDS-18B-EVK. Any Ti employee that can answer this question? That could really be helpfull, since the ev kit is working fine, in my lab.

    Thank you, Savino

  • 0 in reply to savino giusto
    TI__Guru* 93670 points

    LV18B.brdHi Savino,

    Please attached find EVM layout. Please use Allegro Viewer.

    Regards,,nasser

  • 0 in reply to Nasser Mohammadi
    Prodigy 180 points

    Hi nasser, 

    Thank you very much for the EVM layout. Can i ask you the Orcad Capture schematics as well?

    Do you have a layout file with only the SERDES part in it?

    Best regards, Savino

  • 0 in reply to savino giusto
    TI__Guru* 93670 points
    Hi Savino,

    Sorry i checked and we have just pdf version of this schematic. Also, the only board layout we have is the one that i already sent to you.

    Regards,,nasser
  • 0 in reply to Nasser Mohammadi
    Prodigy 180 points

    ok, thank you anyway

    regards, Savino