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XIO2213B Power Sequencing

Bob Fitch
Intellectual 345 points
Other Parts Discussed in Thread: XIO2213B, XIO2001

The implementation guide for the XIO2213B (doc SCPA048 - Oct 2010) states the following for power sequencing:

“When power cycling the XIO2213B, supply sequencing is required to ensure that the output cells have valid inputs from the core when they are powered up or powered down. The 1.5-V, 1.95-V analog, 1.5-V, and 1.95-V digital power supplies must be applied first when powering up the device and removed last when powering down the device. Having stable signal levels from the core logic driving the output cells prevents output driver current and voltage fluctuations when the output cells are powered up or powered down.”

The XIO2213B Data Manual (doc SCPS210E - Oct 2012) in Section 3.1 seems to not even be talking about the power rails for this part and only discusses PCI spec on 1.5V and 3.3V slot power rails and offers no real sequencing info (it looks like that same info that was in the semi-related XIO2001 Data Manual).  No mention of 1.95V.

This is not very clear what this sequencing is relative to or how the various 3.3V power rails fit into this ... especially since on the XIO2213AEVM Evaluation Module it appears to not follow this.  FYI - this is what the EVM does this:

  • 12V power (BUS_POWER) from the PCI Express connector is converted to 3.3V (PHY_POWER) with a LM2574HVM-3.3 switching regulator that is always enabled. So, the 3.3V PHY_POWER is delayed relative to 12V BUS_POWER.
  • 3.3V PHY_POWER drives a 1.95V TPS79301 LDO (enable tied to PHY_POWER so essentially no enable). So, this tracks up/down with PHY_POWER.
  • 3.3V PHY_POWER also drives the PLLVDD_33, AVDD_33, DVDD_33 (same as PHY_POWER) and OSC_VDD rails.  
  • 3.3V power from the PCI Express connector (SYS_3V) is the input/enable on a TPS75215QPWP switching regulator that generates 1.5V
  • SYS_3V is used for 3.3V directly for the power rails VDDA_33 (filtered) and VDD_33 (direct)

Note:  the PCI Express spec does not require any ordering on the power on their connector so SYS_3V could come on first or last -- From the spec:  “There is no specific requirement for power supply sequencing of each of the three power supply rails. They may come up or go down in any order.”

Q1:  Do you have better documentation on exactly what the sequencing requirements and timing relations are for all the power rails on the XIO2213B?

Q2:  If the sequencing is not met then will the device be damaged ... or not function properly?

Thanks!

  • 0
    TI__Guru* 76130 points
    Hello,

    Q1: There is no timing spec, the only requirement is that the 1.5 power rail valid and stable before the 3.3V power rail, by "valid" I mean it has reached its minimum recommended value.

    Q2: The device may not work properly, it won't be damaged.

    I also recommend to connecting GRST# to a 1.5V power-good signal.

    Regards
  • 0 in reply to Elias Villegas M.
    Intellectual 345 points

    Which 3.3V power rails on the XIO2213B does the 1.5V power have to be valid/stable relative to (all of them? ... some of them?)?   FYI - The EVM has two 3.3V regulators ... and the EVM  turns on 1.5V after the 3.3V which comes from the PCI Express slot.

    Why do you recommend that GRST# be tied to the 1.5V power-good?  FYI - GRST# is not connected on the EVM.

    Thanks.

  • 0 in reply to Bob Fitch
    TI__Guru* 76130 points
    Hello,

    Sorry for the confusion, I have reviewed the documentation carefully and have the following comments.
    My last statement is a little bit misleading, there is actually no timing requirement between 1.5V and 3.3V, I said that because some times Customers connect terminal GRST# to the 3.3V and in this case there is indeed a requirement that 1.5V starts first because the core logic is powered by 1.5V and de-asserting GRST# before 1.5V is valid could cause unexpected behavior.

    Please look at the XIO2001 datasheet, the power-up sequence on that Device is what has to be done with the XIO2213B as well, note that the only new item is that we specify that GRST# is de-asserted until both 1.5V and 3.3V are valid.

    I will star a process to update the XIO2213B's datasheet to reflect this.

    Regards
  • 0 in reply to Elias Villegas M.
    Intellectual 345 points

    Is it correct that there is no sequencing requirements for the 1.95V voltage either?

    Since the EVM didn't have GRST# connected at all (the pin is disconnected) I'm assuming PERST# is sufficient to reset the entire XIO2013B part and we can leave GRST# disconnected (i.e., do GRST# and PERST# do the same thing?).

  • 0 in reply to Bob Fitch
    TI__Guru* 76130 points
    Correct, 1.95V has no timing requirement against 1.5V and 3.3V.

    GRST# and PERST# don't do the same thing.
    GRST# shall remain asserted until all the power rails are valid and stable. GRST# could be left floating only if you can assure 1.5V and VDDCORE ramp up before 3.3V.

    Regards
  • 0 in reply to Elias Villegas M.
    Intellectual 345 points
    GRST# is floating on the EVM and 1.5V power can come on after 3.3V. This would seem to contradict what you just said.
  • 0 in reply to Bob Fitch
    TI__Guru* 76130 points
    Hello, thank you for your comments.
    I am aware of the state of the EVM, we will update the datasheet per the above clarifications though.
    Regards
  • 0 in reply to Elias Villegas M.
    Intellectual 345 points
    If we have a reset signal that is always asserted when either the 1.5V or 3.3V power is NOT valid (which is how the PCI slot timing works on its PERST#) and then we tie this signal to both PERST# and GRST# on the XIO2213B ... will that meet the voltage sequencing requirement for 1.5V and 3.3V?

    The exact timing for our reset signal is as following:
    - asserted low for at least 100 msec after both 1.5V and 3.3V power is valid and then deasserts high.
    - If either 1.5V or 3.3V power goes invalid then the reset is immediately assert low.

    Note: we don't care if any state information is preserved when our reset is asserted ... it is always treated as a power-on reset. So, we can reset everything everytime.

    Is there any issue if the 1.5V power is off for a long period of time (for example in a sleep mode) and the 3.3V power is still on as long as we have PERST# and GRST# both asserted on the XIO2213B when 1.5V is off (i.e., there isn't some backdrive from 3.3V into 1.5V inside the XIO2213B)?
  • 0 in reply to Bob Fitch
    TI__Guru* 76130 points
    Hello,

    Your sequencing is correct.
    Yes, it is possible to tie GRST# and PERST# together under the conditions you describe.
    I need to double-check with design about the fail safe question.
    Regards
  • 0 in reply to Elias Villegas M.
    TI__Guru* 76130 points
    Hello,

    I have confirmed that it is not recommended to power 1.5V off while 3.3V is present, this will cause unexpected behavior.
    Regards
  • 0 in reply to Elias Villegas M.
    Intellectual 345 points

    AOK ... we decided to not pursue that (we will have 1.5V will come on first ... then 3.3V).  Thanks.