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TLK10232 - RESET_N pin

Kawai
Guru 19785 points
Other Parts Discussed in Thread: TLK10232

Hi Team,

I would like to ask you that about the hardware RESET.

There is RESET_N pin and must be held Low for at least 10us after device power stabilization.

Do you need to control RESET_N externally other than the case above ? I believe you could use software reset instead of this hardware reset.

Best Regards,

Kawai

  • 0
    TI__Genius 16150 points
    Hi Kawai,

    There different modes to reset the device through software:

    Clause 22 and 45 (Global Control)
    Device Address: 0x1E Register Address: 0x0000
    Bit [15] Global Reset ==> 0 = Normal Operation; 1=Resets TX & RX data path including MDIO registers. Equivalent to asserting RESET_N.

    Only Clause 45 mode (PMA/PMD Registers)
    Device Address: 0x01 Register Address: 0x0000
    Bit [15] RESET ==> 0 = Normal Operation; 1=Global Reset. Resets data path and MDIO registers for all channels. Equivalent to asserting RESET_N.

    Clause 45 (PCS Registers, Valid when device is in 10GBASE-KR mode)
    Device Address: 0x03 Register Address: 0x0000
    Bit [15] PCS_RESET ==> 0 = Normal Operation; 1=Global Reset. Resets data path and MDIO registers for all channels. Equivalent to asserting RESET_N.

    Best Regards!
    Luis Omar Morán Serna
    High Speed Interface Group
    SWAT Team
  • 0 in reply to Luis Omar Moran
    Guru 19785 points

    Hello Luis-san,

    Thanks for the detail explanation to the software reset function.

    Do you recommend to design RESET_N pin to be externally configurable other than at power up sequence ?

    Best Regards,

    Kawai

  • 0 in reply to Kawai
    TI__Genius 16150 points
    Hi Kawai,

    I recommend you to reset the device through the RESET_N pin externally due to TLK10232 LVCMOS I/O are not failsafe (i.e. cannot be driven with the I/O power disabled).

    On the other hand when you initialize the device I suggest to reset the device through GLOBAL_CONTROL_1 (Via Software):
    write 0x8610 to 0x1E.0000 (After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle)


    Best Regards!
    Luis Omar Morán Serna
    High Speed Interface Group
    SWAT Team