Hello again. This time I would like to ask about the internal ESD protection on the TD+/-, RD+/- pins of the DP83848x. My application must withstand severe ESD discharges (even higher than those on IEC61000-4-2 class 4) coming from the copper side. I have already checked snla108a but it doesn't help much in my case. Obviously, a suitable TVS has to be used on the pins to be protected. However, I have to ensure that the residual (clamping) voltage will not harm the PHY pins mentioned above. If not, I am afraid that I have to resort to limiting resistors between the each TVS and the PHY pin.
So I want to run two SPICE simulations: One with the DP83848x alone and a simulated HBM 4kV generator (Rzap = 1.5k, Czap = 120 pF, per datasheet). Then a simulation of the full circuit (incl. the TVS). If the pin current level in the second simulation proves to be equal or lower than the current in the first one (i.e. the 4kV HBM), then a series resistor in not needed.
But, in order to perform these simulations, I need to know the characteristics of the internal protection of the TD and RD pins, that is: a) Is it a 2-diode network tied to the supply rails or a uni/bidirectional zener, b) the associated SPICE parameters of the internal protection (BV, IBV, Rs, Cjo, M, N etc). Is it possible for you to reveal these parameters?
Thank you in advance
