Hello,
Three related (multi-section) questions:
1. How do you optimize the 1 nF to 10 nF range expressed in the datasheet for your design output frequency (given that you will size the caps to match the trace width)? As an example, say the output data rate is 1.28 Gbps and for another application it is 2.4 Gbps.
Do you try to find a cap value that brings 1/2πFC at the data rate closest to zero ohm? Do you consider the resonance frequency between these caps and the trace inductance and other secondary effects?
2. If two assemblies are communicating via a pair of TLK2711-SP transceiver (a transmitter to a receiver 10 meters apart and each using a different power supply), do you use the AC capacitors on the hi-side and the low-side of both the transmitter and receiver ends?
If so, how closely should these 4 capacitors match? If only two caps needed, which side (at the transmitter or receiver) should they reside and how closely should they match? Finally, It is recommended to place the Caps closest to the output connector at the transmitter end - I am assuming this is done to remove any common-mode current due to the entire route before the signal is existed the board, is that correct? Where should the caps at the Receiver end reside, closest to the TLK2711 chip?
3. For reliability, if one cap fails short (or maybe open), do you recommend parallel series cap combinations or will that cause too much signal integrity degradation or loss?
Thanks
-Ali