SN65DSI86 Any limitations on HPW/HBPR, also ASSR support

hamasaki1818

Other Parts Discussed in Thread: SN65DSI86, TEST2

Hiya,

I'm looking at SN65DSI86 to replace a similar-function DSI>eDP bridge from Toshiba and I have some questions.

Toshiba part requires that minimum HPW+HBPR must be >= 48pixels for 4channel eDP transmission. The datasheet for SN65DIS86 doesn't mention anything like that. Is there such limitation, or can I use ex. HPW = 5 and HBPR = 7 or so. HPW = hsync pulse width, HBPR = hsync back porch.

Regarding ASSR, there's following information on the internet: "for Non ASSR panel, need a HW stripping please contact TI to get more information". Any.. more information on that?

Also, I plan to access this part only via the DSI0 (DSI Channel A) configuration registers (I2C will be not-connected). Is there any special settings I need to do prior to this from the DSI master, such as setting LPTIME etc.

over 10 years ago

0 Joel Jimenez0 over 10 years ago

TI__Mastermind 18655 points

Hello,

1. There is no such requirement for HPW and HBPR fields.

2. For using a non-ASSR panel the DIS86 requires that TEST2 pin to be pulled up before the assertion of EN and software program a '1' to bit 0 offset 0x16 at Page 7 followed bye write '0' to bit 0 of offset 0X5A at Page 0.

3. Before assert the EN input you need to set the GPIO[3:0] value correctly based on the clock source (REFCLK or DACP/N). (According to the device PowerUp Sequence ).

Additional info:

Regards,
Joel

0 hamasaki1818 over 10 years ago in reply to Joel Jimenez0

Intellectual 370 points

Hello,

Thanks for the explanation.

About #2 point, can we leave TEST2 pulled up, and if the above register setting is not done, does the IC still work with ASSR-capable panels? Or do we need to have TEST2 on a GPIO and leave it LOW for ASSR panels?

Regarding #3 point, yes, REFCLK will be used, and GPIO[3:0] is already set accordingly.

Thanks!

0 Joel Jimenez0 over 10 years ago in reply to hamasaki1818

TI__Mastermind 18655 points

Hello,

They can leave TEST2 pulled up at all times. ASSR remains enabled until they change bit 0 at offset 0x5A in Page 0. Therefore, Bit 0 = 1 means ASSR enabled.

Regards,
Joel

0 hamasaki1818 over 10 years ago in reply to Joel Jimenez0

Intellectual 370 points

Thanks. PCB off to production to test this.

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SN65DSI86 Any limitations on HPW/HBPR, also ASSR support